Recommended Operating Conditions

Parameter	Min	Typ	Max
Analog supply voltage (AVDD: vdda_bg, vdda_lna, vdda_cmp)	1.8 V	2.5 V	2.8 V
Digital supply voltage (DVDD: dvdd)	1.1 V	1.2 V	1.3 V
Level shifter supply (DVDD2P5: dvdd2p5)	2.25 V	2.5 V	2.75 V
System clock frequency (clk)	40 MHz	80 MHz	160 MHz
System clock duty cycle	45%	50%	55%
SPI clock frequency (sclk)	—	clk/4	40 MHz
Characterization temperature	—	25 °C	—

Caution: Do not exceed the recommended supply voltages. The NYX1-512 chip has no on-chip overvoltage protection. Ensure that supply voltage ramp rates and sequencing do not produce transient overshoot above the recommended maximums. Power supply sequencing requirements (analog before digital, or simultaneous) have not been characterized. Contact Science before designing a sequenced supply.

Power Supply

The NYX1-512 chip has five independent supply rails. All analog rails share a 2.5 V nominal voltage but are separated at the chip to minimize noise coupling between the bias generator, LNA, and comparator domains. The rails can be supplied by independent regulators for optimal noise performance, or by a single regulator if proper decoupling is used.

Rail	Regulator	Voltage	Max Current	Decoupling
vdda_bg	2.5 V LDO	2.5 V	5 mA	4.7 µF + 100 nF
vdda_lna	2.5 V LDO	2.5 V	10 mA	4.7 µF + 100 nF
vdda_cmp	2.5 V LDO	2.5 V	10 mA	4.7 µF + 100 nF
dvdd2p5	2.5 V LDO	2.5 V	5 mA	4.7 µF + 100 nF
dvdd	1.2 V LDO	1.2 V	5 mA	4.7 µF + 100 nF

Place both decoupling capacitors as close to each supply pin as possible.

All ground pins (vssa_bg, vssa_lna, vssa_cmp, dvss, sub) should be connected to a common low-impedance ground. The substrate pin (sub) must be connected to ground — do not leave it floating.

Power supply sequencing: Ensure that all power supplies have reached the nominal voltage level before the RSTB signal is toggled.

FPGA Interface

The NYX1-512 chip requires an FPGA for SPI control and high-speed serial data reception. A microcontroller cannot meet the timing requirements (40 MHz SCLK, 160 Mbps serial data).

Signal Group	Signals	Direction	Notes
SPI	csn, sdin, sclk	FPGA → chip	Drive on falling SCLK edge
SPI	sdout	Chip → FPGA	Sample on falling SCLK edge
System	clk	FPGA → chip	≤ 160 MHz, 50% duty cycle
System	rstb	FPGA → chip	Active low; hold low for ≥ 6 ms at power-up
Serial data	data_ser_out<3:0>	Chip → FPGA	SDR, ≤ 160 Mbps, load ≤ 10 pF
Serial data	wclk_ser_out<3:0>	Chip → FPGA	Word clock, 1/16 of data rate
Test / GPO	digtest_out<2:0>	Chip → FPGA	(Optional) debug only

All digital I/O are 1.2 V CMOS; use a 1.2 V FPGA I/O bank or add level translation. Keep trace lengths matched within each signal group (SPI, serial data).

The system clock (clk) must be generated by the FPGA, and sclk must be in-phase with clk. The simplest method is to divide clk by 4.

FPGA Requirements

Requirement	Minimum
I/O voltage	1.2 V LVCMOS
SPI master	40 MHz SCLK, 32-bit transfers
Serial data rate	160 MHz maximum
Clock output	≤ 160 MHz, < 50 ps rms jitter
Logic resources	< 5k LUT4 avg

Electrode Array Interface

The NYX1-512 chip is designed for flip-chip bonding directly onto an electrode array or interposer substrate. The 512 active electrode bumps are arranged in the center of the die on a 140 µm pitch grid.

Each panel requires at least one external reference electrode connection. For the simplest configuration, connect all reference electrode pins (R1, R2 on each panel) to a single large-area reference electrode in the recording medium.

Analog Test Interface

Three analog test pads (vtest_out<0>, vtest_out<1>, itest_out) are located on the chip edge (Row A/B, pins 24–26). These can be routed to test points on the headstage PCB for bench characterization. They are not required for normal recording operation.