Register Summary

The NYX1-512 contains 101 writable (RAM) registers. Below are the descriptions and default values of all of the registers.

Addr	Name	Group	Default
0x00	d_bgvref	AnaDrive	0x0000
0x01	d_irefdac	AnaDrive	0x0840
0x02–0x0C	d_vdac0–10	AnaDrive	varies
0x0D–0x18	d_idac0–11	AnaDrive	varies
0x19	d_test	AnaDrive	0x0000
0x1A	d_ramp	AnaDrive	0x0006
0x1B	d_eltest	AnaDrive	0x0000
0x1C	d_elref	AnaDrive	0xCCCC
0x1D	d_elbus	AnaDrive	0x0000
0x1E	d_elimp	AnaDrive	0x0000
0x1F	s_sw (LFP)	Nixel	0x1080
0x20	s_sw (Spike)	Nixel	0x1080
0x21	s_lna (LFP)	Nixel	0x0010
0x22	s_lna (Spike)	Nixel	0x0010
0x23–0x32	pd[255:0] (16 regs)	Nixel	0xFFFF
0x33	s_cmp	Nixel	0xAAAA
0x34	N_start_adc	ADC	0x00FA
0x35	N_stop_adc	ADC	0x1324
0x36	gray_adc / rstb_adc	ADC	0x0000
0x37	sel_panel	DigCont	0x0011
0x38	sel_test	DigCont	0x7000
0x39	enable_oe_ser	DigCont	0x0FFF
0x3A	enable_mode_select_hs	DigCont	0xF000
0x3B	chip_port_id_hs	DigCont	0x00E4
0x3C–0x3F	spi_scan_window_size (4 regs)	DigCont	0x4000
0x40–0x43	spi_scan_start_time (4 regs)	DigCont	0x0032
0x44	spi_scan_data	DigCont	0x2301
0x45	enable_adc_timing_limit	DigCont	0x00FF
0x46	dtest_mode_cmp	DigCont	0x00FF
0x47	dtest_data_cmp	DigCont	0x0000
0x48	spi_direct_control	DigCont	0x0000
0x49–0x58	ADC timing set/reset (16 regs)	DigCont	varies
0x59–0x5C	spi_line_time (4 regs)	DigCont	0x1388
0x5D	enable / auto_line_time	DigCont	0x00F0
0x5E	enable_rstb / signal_retime	DigCont	0x01FF
0x5F	spi_gpout	DigCont	0x0000
0x60–0x65	unused (6 regs)	Scratch	0x0000

AnaDrive

ADR	REG NAME	REG INFO / NET NAME	DEF (HEX)	15	14	12	11	10	9	8	7	6	5	4	3	2	1	0
0	d_bgvref[7:0]	BandGap and Vref Settings	0000	‎							test_bg[2:0]			start_bg	pd_bg	pd_ota_vref	pull_down_drv_vref	pull_up_drv_vref
1	d_irefdac[15:0]	Iref Settings	0840	pd_iref	d_iref[7:0]							d_idac[6:0]
2	d_vdac0[12:0]	vdac0_vcm_lna	0908	‎		pd_vdac_0	vdac_0[11:0]
3	d_vdac1[12:0]	vdac1_vncas_lna	0908	‎		pd_vdac_1	vdac_1[11:0]
4	d_vdac2[12:0]	vdac2_vpcas_lna	0908	‎		pd_vdac_2	vdac_2[11:0]
5	d_vdac3[12:0]	vdac3_vcm_pre	0908	‎		pd_vdac_3	vdac_3[11:0]
6	d_vdac4[12:0]	vdac4_vref_int	073A	‎		pd_vdac_4	vdac_4[11:0]
7	d_vdac5[12:0]	vdac5_vref_ramp	0908	‎		pd_vdac_5	vdac_5[11:0]
8	d_vdac6[12:0]	vdac6_vimp	0172	‎		pd_vdac_6	vdac_6[11:0]
9	d_vdac7[12:0]	vdac7_vtest	0172	‎		pd_vdac_7	vdac_7[11:0]
10	d_vdac8[12:0]	vdac8_vref_test	0172	‎		pd_vdac_8	vdac_8[11:0]
11	d_vdac9[12:0]	vdac9_vncas	0908	‎		pd_vdac_9	vdac_9[11:0]
12	d_vdac10[12:0]	vdac10_vpcas	0908	‎		pd_vdac_10	vdac_10[11:0]
13	d_idac0[7:0]	idac0_vnbias_lna	0010	‎							pd_idac_0	idac_0[6:0]
14	d_idac1[7:0]	idac1_vpbias_pre	0010	‎							pd_idac_1	idac_1[6:0]
15	d_idac2[7:0]	idac2_vnbias_d2s	0010	‎							pd_idac_2	idac_2[6:0]
16	d_idac3[7:0]	idac3_i_int	0020	‎							pd_idac_3	idac_3[6:0]
17	d_idac4[7:0]	idac4_ipbias_int	0020	‎							pd_idac_4	idac_4[6:0]
18	d_idac5[7:0]	idac5_ipbias_ramp	0020	‎							pd_idac_5	idac_5[6:0]
19	d_idac6[7:0]	idac6_inbias_vdac0	0050	‎							pd_idac_6	idac_6[6:0]
20	d_idac7[7:0]	idac7_inbias_vdac1_2	0050	‎							pd_idac_7	idac_7[6:0]
21	d_idac8[7:0]	idac8_inbias_vdac3	0050	‎							pd_idac_8	idac_8[6:0]
22	d_idac9[7:0]	idac9_inbias_vdac4	0050	‎							pd_idac_9	idac_9[6:0]
23	d_idac10[7:0]	idac10_inbias_vdac5	0050	‎							pd_idac_10	idac_10[6:0]
24	d_idac11[7:0]	idac11_inbias_vdac6_7_8	0050	‎							pd_idac_11	idac_11[6:0]
25	d_test[10:0]	Analog Test MUX Settings	0000	‎				enable_itest	sel_itest	enable_vtest	sel_vtest1[3:0]				sel_vtest0[3:0]
26	d_ramp[5:0]	RampGen Settings	0006	‎									ramp_test_enable	ramp_pd	ramp_scap[3:0]
27	d_eltest[15:0]	Electrode MUX Settings: Test Electrodes	0000	eltest_3[3:0]			eltest_2[3:0]				eltest_1[3:0]				eltest_0[3:0]
28	d_elref[15:0]	Electrode MUX Settings: Ref Electrodes	CCCC	elref_3[3:0]			elref_2[3:0]				elref_1[3:0]				elref_0[3:0]
29	d_elbus[15:0]	Electrode MUX Settings: Test Read Busses	0000	elbus_3[3:0]			elbus_2[3:0]				elbus_1[3:0]				elbus_0[3:0]
30	d_elimp[7:0]	Electrode MUX Settings: Impedance Read Busses	0000	‎							elimp_3[1:0]		elimp_2[1:0]		elimp_1[1:0]		elimp_0[1:0]

Nixel

ADR	REG NAME	REG INFO / NET NAME	DEF (HEX)	15	13	11	10	9	7	5	3	1
31	s_sw[15:0]	Nixel-BOT Input Switches	1080	spe_BOT[4:0]			sne_BOT[4:0]			simp_BOT[5:0]
32	s_sw[31:16]	Nixel-TOP Input Switches	1080	spe_TOP[4:0]			sne_TOP[4:0]			simp_TOP[5:0]
33	s_lna[15:0]	LNA-BOT HP + LP Filter Corner Selection	0010	lp_BOT[3:0]		hp_BOT[7:0]					gain_cap_BOT[3:0]
34	s_lna[31:16]	LNA-TOP HP + LP Filter Corner Selection	0010	lp_TOP[3:0]		hp_TOP[7:0]					gain_cap_TOP[3:0]
35	pd[15:0]	Power-Down for 16 nixels, Start Index = 0	FFFF	pd[15:0]
36	pd[31:16]	Power-Down for 16 nixels, Start Index = 16	FFFF	pd[31:16]
37	pd[47:32]	Power-Down for 16 nixels, Start Index = 32	FFFF	pd[47:32]
38	pd[63:48]	Power-Down for 16 nixels, Start Index = 48	FFFF	pd[63:48]
39	pd[79:64]	Power-Down for 16 nixels, Start Index = 64	FFFF	pd[79:64]
40	pd[95:80]	Power-Down for 16 nixels, Start Index = 80	FFFF	pd[95:80]
41	pd[111:96]	Power-Down for 16 nixels, Start Index = 96	FFFF	pd[111:96]
42	pd[127:112]	Power-Down for 16 nixels, Start Index = 112	FFFF	pd[127:112]
43	pd[143:128]	Power-Down for 16 nixels, Start Index = 128	FFFF	pd[143:128]
44	pd[159:144]	Power-Down for 16 nixels, Start Index = 144	FFFF	pd[159:144]
45	pd[175:160]	Power-Down for 16 nixels, Start Index = 160	FFFF	pd[175:160]
46	pd[191:176]	Power-Down for 16 nixels, Start Index = 176	FFFF	pd[191:176]
47	pd[207:192]	Power-Down for 16 nixels, Start Index = 192	FFFF	pd[207:192]
48	pd[223:208]	Power-Down for 16 nixels, Start Index = 208	FFFF	pd[223:208]
49	pd[239:224]	Power-Down for 16 nixels, Start Index = 224	FFFF	pd[239:224]
50	pd[255:240]	Power-Down for 16 nixels, Start Index = 240	FFFF	pd[255:240]
51	s_cmp[15:0]	Digital Output Mux Select for nixel	AAAA	s_cmp_3_TOP[1:0]	s_cmp_3_BOT[1:0]	s_cmp_2_TOP[1:0]		s_cmp_2_BOT[1:0]	s_cmp_1_TOP[1:0]	s_cmp_1_BOT[1:0]	s_cmp_0_TOP[1:0]	s_cmp_0_BOT[1:0]

The s_cmp register controls the digital output MUX for each nixel group, per panel, for both spike (TOP) and LFP (BOT) nixel rows.

Code	Mode	Description
00	Comp Output	Select comparator output + gated d_test
01	Latched Comp	Select latched comparator output + gated d_test
10	D-test bypass	Select d_test output, bypassing comparator (hardware default)
11	—	Undefined

Note: The hardware default 0xAAAA bypasses the comparator entirely. To receive neural data, you must write 0x0000 to this register to select the actual comparator output (mode 00).

ADC

ADR	REG NAME	REG INFO / NET NAME	DEF (HEX)	15	7	3
52	N_start_adc[15:0]	Start Value for ADC Counter, glb setting	00FA	N_start_ADC[15:0]
53	N_stop_adc[15:0]	Stop Value for ADC Counters, glb setting	1324	N_stop_ADC[15:0]
54	{gray_adc[3:0], rstb_adc[3:0]}	Gray/Bin Count Modes + ADC_Reset_Bar	0000	‎	gray_adc[3:0]	rstb_adc[3:0]

ADC Reset Release

After power-up, you must release the ADC reset by writing to register 0x36. Gray code counting reduces digital switching noise from the ADC counter distribution coupling into the analog domain.

Value	gray_adc	rstb_adc	Effect
0x00FF	0xF (Gray)	0xF (released)	Gray code counting, all ADCs active
0x000F	0x0 (Binary)	0xF (released)	Binary counting, all ADCs active

DigCont

ADR	REG NAME	REG INFO / NET NAME	DEF (HEX)	15	14	11	10	9	8	7	6	5	4	3	2	1	0
55	sel_panel[7:0]	Panel Select for Dig. Test Outs and Ramp Controls	0011	‎						sel_panel_test_outputs[3:0]				sel_panel_ramp_control[3:0]
56	sel_test[14:0]	Select Active Dig. Test Outputs, 4-bit x 3 Mux Select Signals, global for all Panels	7000	‎	enable_digtest_out[2:0]	select_digtest_out_2[3:0]				select_digtest_out_1[3:0]				select_digtest_out_0[3:0]
57	enable_oe_ser[11:0]	Enable Serializer for Panels, ON Signal for Data /Wclk for each Panel	0FFF	‎		enable_serializer[3:0]				enable_wclk[3]	enable_data[3]	enable_wclk[2]	enable_data[2]	enable_wclk[1]	enable_data[1]	enable_wclk[0]	enable_data[0]
58	enable_mode_select_hs[15:0]	Enable Horizontal_Scanner, Mode Select Horizontal_Scanner	F000	enable_hs[3:0]		test_mode_select_hs_3[3:0]			test_mode_select_hs_2[3:0]			test_mode_select_hs_1[3:0]			test_mode_select_hs_0[3:0]
59	chip_port_id_hs[15:0]	8-bit Chip ID (default h00), and 4-Port IDs for Panels. 8-bit Port IDs defaults are: 11, 10, 01, 00 (default hE4)	00E4	chip_id[7:0]						port_id_3[1:0]		port_id_2[1:0]		port_id_1[1:0]		port_id_0[1:0]
60	spi_scan_window_size[15:0]	Windowing Register for Panel-0: 8-bit Column Count, 8-bit Column Start	4000	column_count_0[7:0]						column_start_0[7:0]
61	spi_scan_window_size[31:16]	Windowing Register for Panel-1: 8-bit Column Count, 8-bit Column Start	4000	column_count_1[7:0]						column_start_1[7:0]
62	spi_scan_window_size[47:32]	Windowing Register for Panel-2: 8-bit Column Count, 8-bit Column Start	4000	column_count_2[7:0]						column_start_2[7:0]
63	spi_scan_window_size[63:48]	Windowing Register for Panel-3: 8-bit Column Count, 8-bit Column Start	4000	column_count_3[7:0]						column_start_3[7:0]
64	spi_scan_start_time[15:0]	Horizontal Scanner Start Time for Panel-0	0032	scan_start_time_0[15:0]
65	spi_scan_start_time[31:16]	Horizontal Scanner Start Time for Panel-1	0032	scan_start_time_1[15:0]
66	spi_scan_start_time[47:32]	Horizontal Scanner Start Time for Panel-2	0032	scan_start_time_2[15:0]
67	spi_scan_start_time[63:48]	Horizontal Scanner Start Time for Panel-3	0032	scan_start_time_3[15:0]
68	spi_scan_data[15:0]	SPI Scan Data: Static Test Data from SPI (for the Last MUX in Data Path, Default h2301, which is Prod ID for ASIC01	2301	spi_scan_data[15:0]
69	enable_adc_timing_limit[7:0]	Enable for ADC Timing Generators in DigCont and Enable Count Limit for ADC Counters in DigRecord	00FF	‎						enable_adc_timing[3:0]				enable_adc_count_limit[3:0]
70	dtest_mode_cmp[7:0]	8-bit Mode select for D-test Signal Generation for nixel Comps. 3-bit per Panel.	00FF	‎						dtest_mode_cmp_3[1:0]		dtest_mode_cmp_2[1:0]		dtest_mode_cmp_1[1:0]		dtest_mode_cmp_0[1:0]
71	dtest_data_cmp[11:0]	12-bit dtest_data from SPI Register	0000	‎		dtest_data_cmp_3[2:0]			dtest_data_cmp_2[2:0]			dtest_data_cmp_1[2:0]			dtest_data_cmp_0[2:0]
72	spi_direct_control[15:0]	16-bit SPI Direct Control Register for all the on-chip generated timing signals, mainly for testing purposes	0000	enable_spi_direct_control[4:0]			start_adc_direct	enable_cmp_direct	clear_cmp_direct	dtest_cmp_direct[2:0]			phi_sh_direct[2:0]			enable_ramp_direct	rst_ramp_direct
73	spi_set_rst_ramp[15:0]	Timing: SET_RST_RAMP	0032	spi_set_rst_ramp[15:0]
74	spi_reset_rst_ramp[15:0]	Timing: RESET_RST_RAMP	012C	spi_reset_rst_ramp[15:0]
75	spi_set_enable_ramp[15:0]	Timing: SET_ENABLE_RAMP	00FA	spi_set_enable_ramp[15:0]
76	spi_reset_enable_ramp[15:0]	Timing: RESET_ENABLE_RAMP	12F2	spi_reset_enable_ramp[15:0]
77	spi_set_phi_sh[15:0]	Timing: SET_PHI_SH	00C8	spi_set_phi_sh[15:0]
78	spi_reset_phi_sh[15:0]	Timing: RESET_PHI_SH	1324	spi_reset_phi_sh[15:0]
79	spi_set_phi_rstb[15:0]	Timing: SET_PHI_RSTB	0096	spi_set_phi_rstb[15:0]
80	spi_reset_phi_rstb[15:0]	Timing: RESET_PHI_RSTB	1356	spi_reset_phi_rstb[15:0]
81	spi_set_dtest_cmp[15:0]	Timing: SET_DTEST_CMP	0096	spi_set_dtest_cmp[15:0]
82	spi_reset_dtest_cmp[15:0]	Timing: RESET_DTEST_CMP	00C8	spi_reset_dtest_cmp[15:0]
83	spi_set_clear_cmp[15:0]	Timing: SET_CLEAR_CMP	0032	spi_set_clear_cmp[15:0]
84	spi_reset_clear_cmp[15:0]	Timing: RESET_CLEAR_CMP	0064	spi_reset_clear_cmp[15:0]
85	spi_set_enable_cmp[15:0]	Timing: SET_ENABLE_CMP	015E	spi_set_enable_cmp[15:0]
86	spi_reset_enable_cmp[15:0]	Timing: RESET_ENABLE_CMP	12C0	spi_reset_enable_cmp[15:0]
87	spi_set_start_adc[15:0]	Timing: SET_START_ADC	00FA	spi_set_start_adc[15:0]
88	spi_reset_start_adc[15:0]	Timing: RESET_START_ADC	12F2	spi_reset_start_adc[15:0]
89	spi_line_time[15:0]	LINE TIME REGISTER for Panel-0. It is suggested to have same LINE time for all Panels.	1388	spi_line_time[15:0]
90	spi_line_time[31:16]	LINE TIME REGISTER for Panel-1. It is suggested to have same LINE time for all Panels.	1388	spi_line_time[31:16]
91	spi_line_time[47:32]	LINE TIME REGISTER for Panel-2. It is suggested to have same LINE time for all Panels.	1388	spi_line_time[47:32]
92	spi_line_time[63:48]	LINE TIME REGISTER for Panel-3. It is suggested to have same LINE time for all Panels.	1388	spi_line_time[63:48]
93	{enable_line_time[3:0], auto_line_time[3:0]}	8-bit ENABLE_TRIGGER_LINE_TIME_REGISTER: Enables all Panels by Default, Expects SPI AUTO Trigger	00F0	‎						enable_line_time[3:0]				auto_line_time[3:0]
94	{enable_rstb_retime[4:0], enable_signal_retime[3:0]}	9-bit ENABLE_RSTB_SIGNAL_REGISTER. All RSTB and SIGNAL Retime functions are ON by Default.	01FF	‎					enable_rstb_retime[4:0]					enable_signal_retime[3:0]
95	spi_gpout[2:0]	3-bit SPI_GPOUT REGISTER. Use Reg#55 to configure to use SPI_GPOUT for digtest_out[2:0]	0000	‎											spi_gpout[2:0]

Unused

ADR	REG NAME	REG INFO / NET NAME	15
96	unused_register0[15:0]	Can be used for SPI R/W Testing	unused_register0[15:0]
97	unused_register1[15:0]	Can be used for SPI R/W Testing	unused_register1[15:0]
98	unused_register2[15:0]	Can be used for SPI R/W Testing	unused_register2[15:0]
99	unused_register3[15:0]	Can be used for SPI R/W Testing	unused_register3[15:0]
100	unused_register4[15:0]	Can be used for SPI R/W Testing	unused_register4[15:0]
101	unused_register5[15:0]	Can be used for SPI R/W Testing	unused_register5[15:0]

AnaDrive Supplemental Detail

0x00 — Bandgap and Vref Startup — Default: 0x0000

After reset, the bandgap is enabled (pd_bg=0) but not started (start_bg=0). The production start sequence writes 0x0010 (start_bg=1) as the first command.

Note: The required delay between pd_bg deassertion and start_bg assertion, and the settling time before DAC outputs are valid.

0x02–0x0C — Voltage DACs — Default: varies

DAC transfer function: output voltage = DAC code × 540 µV/code.

Practical output range: the DAC output is clipped by the output buffer to 0.2 – 2.0 V, corresponding to codes 371 – 3703 (0x173–0xE77).

Addr	Register	Function	Default	Default Output
0x02	d_vdac0	vcm_lna — LNA common mode	0x0908	1.250 V
0x03	d_vdac1	vncas_lna — LNA NMOS cascode	0x0908	1.250 V
0x04	d_vdac2	vpcas_lna — LNA PMOS cascode	0x0908	1.250 V
0x05	d_vdac3	vcm_pre — Preamp common mode	0x0908	1.250 V
0x06	d_vdac4	vref_int — ADC ramp start voltage	0x073A	1.000 V
0x07	d_vdac5	vref_ramp — ADC ramp midpoint	0x0908	1.250 V
0x08	d_vdac6	vimp — Impedance drive voltage	0x0172	0.200 V
0x09	d_vdac7	vtest — Test signal voltage	0x0172	0.200 V
0x0A	d_vdac8	vref_test — Test reference voltage	0x0172	0.200 V
0x0B	d_vdac9	vncas — Global NMOS cascode	0x0908	1.250 V
0x0C	d_vdac10	vpcas — Global PMOS cascode	0x0908	1.250 V

0x0D–0x18 — Current DACs — Default: varies

The NYX1-512 has 12 current DACs, each with a 7-bit value and a power-down bit.

iDAC transfer function: output current = code × 500 nA/code.

Range: 0–63.5 µA (codes 0–127).

Addr	Register	Function	Default	Default Output
0x0D	d_idac0	vnbias_lna — LNA NMOS bias	0x0010	8 µA
0x0E	d_idac1	vpbias_pre — Preamp PMOS bias	0x0010	8 µA
0x0F	d_idac2	vnbias_d2s — Diff-to-single bias	0x0010	8 µA
0x10	d_idac3	i_int — Integrator current	0x0020	16 µA
0x11	d_idac4	ipbias_int — Integrator PMOS bias	0x0020	16 µA
0x12	d_idac5	ipbias_ramp — Ramp PMOS bias	0x0020	16 µA
0x13–0x18	d_idac6–d_idac11	vDAC NMOS biases (inbias_vdac_0 – inbias_vdac_8)	0x0050	40 µA

Note: iDAC0 (vnbias_lna) affects effective LNA gain. Production firmware sets iDAC0 to 0x0020 (vs. default 0x0010). Higher bias current reduces gain relative to the theoretical value.

0x19 — d_test[10:0] — Analog Test MUX Settings — Default: 0x0000

Bits	Field	Description
15:11	—	Unused
10	enable_itest	Enable current test output
9	sel_itest	Select itest source (0 = copy of iref, 1 = copy of idac_11)
8	enable_vtest	Enable voltage test outputs
7:4	sel_vtest1[3:0]	Select source for vtest_out[1]
3:0	sel_vtest0[3:0]	Select source for vtest_out[0]

Code	vtest_out[1]	vtest_out[0]
0	vcm_lna	vnbias_lna
1	vncas_lna	vpbias_pre
2	vpcas_lna	vnbias_d2s
3	vcm_pre	vssa
4	vref_int	vssa
5	vref_ramp	vssa
6	vimp	vimp_read
7	vtest	vref_test
8	vncas	vssa
9	vpcas	vdda
10	vtest_vbg	sub
11	vtest_vtemp	sub
12	vtest_vref	vssa
13	vssa	vssa
14	vramp_pos	vramp_neg
15	vtest_pos	vtest_neg

0x1A — d_ramp[5:0] — Ramp Generator Settings — Default: 0x0006

At reset, the ramp generator is enabled with scap = 6 and test mode off.

Bits	Field	Description
15:6	—	Unused
5	ramp_test_enable	Enable ramp test mode
4	ramp_pd	Power-down ramp generator
3:0	ramp_scap[3:0]	Ramp integration capacitor select

0x1B — d_eltest[15:0] — Test Electrode MUX — Default: 0x0000

Controls test electrode routing for each panel independently.

Bits	Field	Description
15:12	eltest_3[3:0]	Panel 3 test electrode MUX
11:8	eltest_2[3:0]	Panel 2 test electrode MUX
7:4	eltest_1[3:0]	Panel 1 test electrode MUX
3:0	eltest_0[3:0]	Panel 0 test electrode MUX

Value	Connection
0b0000	High-Z (disconnected)
0b0011	{vdac7_vtest, vdac8_vref_test}
0b1100	elt[1:0] (external test electrodes)

0x1C — d_elref[15:0] — Reference Electrode MUX — Default: 0xCCCC

At reset, all panels are connected to external references. Controls reference electrode routing for each panel independently.

Bits	Field	Description
15:12	elref_3[3:0]	Panel 3 reference electrode MUX
11:8	elref_2[3:0]	Panel 2 reference electrode MUX
7:4	elref_1[3:0]	Panel 1 reference electrode MUX
3:0	elref_0[3:0]	Panel 0 reference electrode MUX

Default: 0xCCCC — all panels connected to external references.

Value	Reference Source
0b0000	High-Z (floating)
0b0011	Internal: {vdac7_vtest, vdac8_vref_test}
0b1100	External: elr[1:0] reference electrodes

0x1D — d_elbus[15:0] — Test Read Bus MUX — Default: 0x0000

Routes test or reference bus signals to the vtest_pos / vtest_neg output pads. Only one panel's bus may be active at a time.

Bits	Field	Description
15:12	elbus_3[3:0]	Panel 3 bus MUX
11:8	elbus_2[3:0]	Panel 2 bus MUX
7:4	elbus_1[3:0]	Panel 1 bus MUX
3:0	elbus_0[3:0]	Panel 0 bus MUX

Value	Bus Connection
0b0000	High-Z
0b0011	elt_glb[1:0] (test electrode bus)
0b1100	elr_glb[1:0] (reference electrode bus)

0x1E — d_elimp[7:0] — Impedance Bus MUX — Default: 0x0000

Routes impedance drive and read signals. Only one panel's impedance bus may be active at a time.

Bits	Field	Description
15:8	—	Unused
7:6	elimp_3[1:0]	Panel 3: {read, drive}
5:4	elimp_2[1:0]	Panel 2: {read, drive}
3:2	elimp_1[1:0]	Panel 1: {read, drive}
1:0	elimp_0[1:0]	Panel 0: {read, drive}

Value	Connection
0b00	High-Z (both disconnected)
0b01	Drive only (eli_drive_glb = vimp_drive)
0b11	Drive + Read (eli_drive_glb + eli_read_glb = vimp_read)

Nixel Registers Supplemental Detail

These registers configure the 256 nixels: input switch matrix, LNA gain/bandwidth, power-down, and comparator output MUX.

0x1F — s_sw[15:0] — Nixel Input Switches (LFP / Bottom Nixels) — Default: 0x1080

Configures the input switch matrix for the bottom row nixels (LFP nixels, indices 0–3 in each panel).

At reset: spe=0b00010 (ela<1>), sne=0b00010 (ela<0>), simp=0. See Configure LNA Inputs for full switch encoding.

Bits	Field	Signal	Description
15:11	spe_BOT[4:0]	—	Positive LNA input switch (one-hot)
10:6	sne_BOT[4:0]	—	Negative LNA input switch (one-hot)
5	simp_BOT[5:0]	eli_drive_ela1	Drive impedance signal to ela<1>
4		eli_drive_ela0	Drive impedance signal to ela<0>
3		eli_read_ela1	Read impedance from ela<1>
2		eli_read_ela0	Read impedance from ela<0>
1		eli_drive_glb	Connect to global impedance drive bus
0		eli_read_glb	Connect to global impedance read bus

Bits [1:0] of simp set the series capacitor value used during impedance measurement.

simp[1:0]	Spike Nixels	LFP Nixels
0b00	Floating (disconnected)	Floating (disconnected)
0b01	0.42 pF	4.14 pF
0b10	1.32 pF	10.0 pF
0b11	1.74 pF	14.14 pF

When a nixel is powered down (pd=1 in registers 0x23–0x32), its switch and LNA registers are forced to zero by hardware.

0x20 — s_sw[31:16] — Nixel Input Switches (Spike / Top Nixels) — Default: 0x1080

Same format as 0x1F but applies to spike nixels (indices 4–63 in each panel).

0x21 — s_lna[15:0] — LNA Configuration (LFP / Bottom Nixels) — Default: 0x0010

Configures LNA gain and filter bandwidth for the bottom row nixels (LFP nixels, indices 0–3 in each panel).

Bits	Field	Description
15:12	lp_BOT[3:0]	Low-pass filter corner select (thermometer coded)
11:4	hp_BOT[7:0]	High-pass filter corner / feedback resistor select (one-hot)
3:0	gain_cap_BOT[3:0]	Gain capacitor select

gain_cap [3:0]

The gain_cap field selects the feedback capacitor. Gain = input capacitance (6.8 pF) / feedback capacitance.

Code	Feedback Cap (fF)	Gain (V/V)	Input-Referred Noise (µV rms)	High-Pass Corner (Hz)
0	34	200.0	4.5	456.7
1	68	100.0	—	228.3
2	102	66.7	—	152.2
3	136	50.0	—	114.2
4	170	40.0	—	91.3
5	204	33.3	—	76.1
6	238	28.6	—	65.2
7	272	25.0	—	57.1
8	306	22.2	—	50.7
9	340	20.0	—	45.7
10	374	18.2	—	41.5
11	408	16.7	—	38.1
12	442	15.4	—	35.1
13	476	14.3	—	32.6
14	510	13.3	—	30.4
15	544	12.5	27.0	28.5

high-pass filter hp[7:0] — one-hot encoded

The high-pass corner frequency is set by f_hp = 1 / (2π × R_fb × C_fb), where R_fb is one-hot encoded from 10.25–82.00 GΩ and C_fb varies from 34–544 fF.

Code	Feedback R (GΩ)
0x00	High-Z (infinite)
0x01	10.25 (default)
0x02	20.50
0x04	30.75
0x08	41.00
0x10	51.25
0x20	61.50
0x40	71.75
0x80	82.00

low-pass filter lp[3:0] — thermometer coded

The lp field uses thermometer coding; only these 5 values are valid.

Code	Pattern	Effect
0x0	0000	Highest LP corner (lowest bias current)
0x1	0001	—
0x3	0011	—
0x7	0111	—
0xF	1111	Lowest LP corner (highest bias current)

low-pass capacitor values lp[3:0]

The lp field also sets the series capacitor value used in the low-pass filter circuit.

Code	C_diff (pF)	C_se (pF)	C_eff per input (pF)
0	0	0	0
1	1.054	0.844	2.952
3	2.108	1.688	5.904
7	3.162	2.635	8.959
15	4.216	4.035	12.467

validated gain/bandwidth configurations

The following configurations have been validated.

HP (Hz)	LP (Hz)	lp	hp	gain_cap	Effective Gain (V/V)
457	13489	0x0	0x01	0	138
154	13489	0x0	0x04	0	179
92	13489	0x0	0x10	0	200
57	13489	0x0	0x80	0	200
57	4365	0x1	0x80	0	201
66	13489	0x0	0x40	0	198
29	25700	0x0	0x40	1	102
33	25700	0x0	0x80	1	102
33	13489	0x1	0x80	1	102
4	25700	0xF	0x80	1	102
19	20400	0xF	0x80	2	67
12	20400	0xF	0x80	4	40
7	20400	0xF	0x80	7	23
4	20400	0xF	0x80	15	13

0x22 — s_lna[31:16] — LNA Configuration (Spike / Top Nixels) — Default: 0x0010

Same format as 0x21 but applies to spike nixels (indices 4–63 in each panel).

LNA Programming for Low-Power

Gain, High-Pass, Low-Pass programmable features. Simulation results, C_load = 1.00 pF.

‎					i_bias = 0.50 µA						i_bias = 0.10 µA
Sweep	Sim	Gain[3:0]	HP[7:0]	LP[3:0]	Peak Gain 0.5µA (V/V)	Vout_noise 0.5µA (µV rms)	HP Corner 0.5µA (Hz)	LP Corner 0.5µA (KHz)	Gain Diff 0.5µA (V/V)	Vin Noise 0.5µA (µV rms)	Peak Gain 0.1µA (V/V)	Vout_noise 0.1µA (µV rms)	HP Corner 0.1µA (Hz)	LP Corner 0.1µA (KHz)	Gain Diff 0.1µA (V/V)	Vin Noise 0.1µA (µV rms)
Gain and HP	1	0000	1000_0000	0000	100.4	1613.0	57.500	13.490	200.8	8.033	100.4	1846	57.544	3.311	200.8	9.193
	2	0001	1000_0000	0000	51.1	1110	29.500	25.700	102.2	10.861	—	—	—	—	—	—
	3	0010	1000_0000	0000	34.3	893	19.900	37.150	68.6	13.017	—	—	—	—	—	—
	4	0100	1000_0000	0000	20.7	677	12.000	60.200	41.4	16.353	—	—	—	—	—	—
	5	1000	1000_0000	0000	11.5	489.2	6.790	97.700	23.0	21.270	—	—	—	—	—	—
	6	1111	1000_0000	0000	6.5	346.8	3.800	151.400	13.0	26.718	6.5	400.6	3.800	37.500	13.0	30.863
	7	0000	0000_0001	0000	69.0	1268	457.000	13.489	137.9	9.195	68.8	1458	467.735	3.311	137.6	10.597
	8	0001	0000_0001	0000	41.5	965.5	239.883	25.119	82.9	11.641	—	—	—	—	—	—
	9	0010	0000_0001	0000	29.7	807.3	158.490	37.154	59.3	13.609	—	—	—	—	—	—
	10	0100	0000_0001	0000	18.9	633.3	95.499	60.256	37.8	16.763	—	—	—	—	—	—
	11	1000	0000_0001	0000	10.9	469.9	53.700	95.499	21.9	21.464	—	—	—	—	—	—
	12	1111	0000_0001	0000	6.3	342.2	30.199	151.356	12.6	27.137	6.3	394.5	30.199	37.154	12.6	31.295
	13	0000	0000_0001	1111	68.9	574.7	457.080	1.445	137.8	4.171	68.5	617.7	467.735	0.354	137.0	4.509
	14	0001	0000_0001	1111	41.5	438	239.883	2.818	82.9	5.283	—	—	—	—	—	—
	15	0010	0000_0001	1111	29.6	367.7	158.489	4.169	59.3	6.203	—	—	—	—	—	—
	16	0100	0000_0001	1111	18.9	291.9	95.499	6.761	37.8	7.730	—	—	—	—	—	—
	17	1000	0000_0001	1111	10.9	223	53.703	12.022	21.9	10.192	—	—	—	—	—	—
	18	1111	0000_0001	1111	6.3	170.8	30.199	19.953	12.6	13.556	6.3	186.5	30.199	4.898	12.6	14.802
HP	19	0000	0000_0010	0000	83.3	1415	234.423	13.489	166.6	8.493	83.2	1625	234.423	3.311	166.4	9.766
	20	0000	0000_0100	0000	89.8	1482	154.882	13.489	179.5	8.256	—	—	—	—	—	—
	21	0000	0000_1000	0000	93.5	1524	114.815	13.489	187.0	8.151	—	—	—	—	—	—
	22	0000	0001_0000	0000	96.0	1554	92.599	13.489	192.0	8.094	—	—	—	—	—	—
	23	0000	0010_0000	0000	97.8	1578	77.177	13.489	195.7	8.064	—	—	—	—	—	—
	24	0000	0100_0000	0000	99.3	1597	66.069	13.489	198.5	8.044	99.4	1828	66.069	3.311	198.8	9.195
	25	1111	0000_0010	0000	6.4	345.3	14.791	154.882	12.8	26.977	6.4	398.2	14.791	38.019	12.8	31.109
	26	1111	0000_0100	0000	6.4	346.2	10.000	154.882	12.9	26.879	—	—	—	—	—	—
	27	1111	0000_1000	0000	6.5	346.6	7.586	151.356	12.9	26.827	—	—	—	—	—	—
	28	1111	0001_0000	0000	6.5	346.8	6.026	151.356	12.9	26.801	—	—	—	—	—	—
	29	1111	0010_0000	0000	6.5	346.9	5.012	151.356	13.0	26.767	—	—	—	—	—	—
	30	1111	0100_0000	0000	6.5	346.9	4.266	151.356	13.0	26.738	6.5	400.5	4.266	37.154	13.0	30.869
LP	31	0000	1000_0000	0001	100.6	1087	57.544	4.365	201.2	5.403	100.7	1206	58.880	1.071	201.4	5.988
	32	0000	1000_0000	0011	100.7	944.2	58.884	2.630	201.4	4.688	—	—	—	—	—	—
	33	0000	1000_0000	0111	100.7	873.4	57.544	1.862	201.3	4.338	—	—	—	—	—	—
	34	0000	1000_0000	1111	100.8	829.8	57.544	1.445	201.5	4.118	100.7	881.6	57.544	0.355	201.4	4.378
	35	1111	1000_0000	0001	6.5	236	3.800	57.544	13.0	18.182	6.5	267.8	3.800	14.125	13.0	20.625
	36	1111	1000_0000	0011	6.5	200.5	3.800	35.481	13.0	15.447	6.5	224.5	3.802	8.709	13.0	17.296
	37	1111	1000_0000	0111	6.5	182.2	3.800	25.704	13.0	14.037	6.5	201.9	3.800	6.309	13.0	15.555
	38	1111	1000_0000	1111	6.5	170.8	3.800	20.400	13.0	13.159	6.5	187.7	3.800	4.899	13.0	14.461

On-Chip Registers