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Overview

Getting Started

Gateware

Driver

CLI Reference

Board Profiles

Axon Peripheral SDK

The Axon Peripheral SDK provides the tools to connect custom ASICs to Science headstages. Each Axon Peripheral consists of a SystemVerilog FPGA module to interface the ASIC with the Axon Controller FPGA, and a software-level C++ driver which runs directly on the headstage.

  • Axon Peripherals currently only support peripherals which extend the BroadbandSource class, like the NYX1-512 chip. Support for other peripheral classes, like Spike Source, and Stimulation sources will be added in the future.
  • Each peripheral will have an ID between 0xF001–0xFFFE. The peripheral ID must be identical across gateware and driver code.
  • The gateware code runs on the Axon Controller FPGA (built into the FPGA bitstream (.bit) by Radiant) and uses SystemVerilog to receive chip samples, frame them, and pass them to the SDK to deliver to the host.
  • The driver code runs on the headstage CPU and uses a C++ plugin (.so) to configure your chip, parse the frames the gateware sends, and present the results as actionable data.

Requirements

To use this SDK, you need:

  • A Science headstage connected to an SDK-supported probe, reachable on your network.
  • synapsectl installed on your machine — pip install science-synapse.
  • Docker running locally. The build runs Lattice Radiant and a cross-compiler inside containers, so you do not install either yourself.
  • A Lattice Radiant license — use the Lattice Software Licensing for instructions on how to get one. Set the local environment variable LM_LICENSE_FILE to a license file path or a port@host server (e.g. export LM_LICENSE_FILE=7788@your-license-host). Gateware builds will abort immediately if it is unset.

Example Peripheral

To get started, Science provides the axon_test_source example peripheral, which contains FPGA and C++ code to read data from a custom peripheral. The example peripheral generates synthetic neural data directly on the FPGA, and streams it through the SDK data path to the headstage. Note: the example code does not interface with a real ASIC.

Navigate to Getting Started to build and deploy the example peripheral. Once it runs, replace the example's code with your own— see Gateware and Driver for detailed usage instructions.