The Nixel 512™ chip runs on dual supply voltages of 1.2 V for digital blocks and 2.5 V for analog blocks. It uses 16-bit digital data paths internally and has four serial data ports with a 16:1 serialization ratio to send out the digital recording results. Each port has a dedicated word clock to indicate the word boundaries in the serial data stream.
The Nixel 512 chip has five digital inputs and twelve digital outputs (I/Os) connected to the world using 1.2 V CMOS I/O buffers and powered with the 1.2 V digital supply of the chip. The chip also has 3-bit general purpose data outputs (GPOs) that can be controlled over SPI if needed.
Digital I/Os
| No. | Input name | Output name | Type | Specification |
|---|---|---|---|---|
| 1 | System | rstb | 1.2V CMOS Input | Active low asynchronous reset |
| 2 | clk | System clock, ≤ 160MHz, 50% duty cycle | ||
| 3 | 4-wire SPI | csn | Active low chip select input for SPI | |
| 4 | sdin | Serial data input for SPI | ||
| 5 | sclk | Serial clock for SPI, sclk freq = 1/4 of clk | ||
| 6 | sdout | 1.2V CMOS Ouput | Serial data output of SPI | |
| 7–10 | Serial data ports | data_ser_out<3:0> | Serial data port for digitized nixels | |
| 11–14 | wclk_ser_out<3:0> | Word clock for serial data port | ||
| 15–17 | Test / GPO | digtest_out<3:0> | Digital test outputs, can be hooked to SPI |
The Nixel 512 chip uses a standard 4-wire SPI interface to program and control the chip, with active low chip select (csn), serial data input (sdin), serial clock (sclk), and serial data output (sdout). SPI interface uses 32-bit words, composed of an 8-bit command (<31:24>), an 8-bit address (<23:16>), and an 16-bit data (<15:0>) and sends the most-significant-bit (MSB) first. Since SPI operates at the rising edge of sclk, csn and sdin are applied at the falling edge of the sclk. Likewise, sdout from the SPI will be updated at the rising edge of the sclk, therefore it should be captured by the external electronics at the falling edge of sclk.
SPI timing takes 32 sclk cycles to enter the 32-bit SPI words into the input shift register of the SPI when csn is LOW. When csn is HIGH, it takes an additional 16 sclk cycles for the SPI controller to decode the SPI commands and read or write to the SPI registers. Including this idle time, an SPI operation will take 48 sclk cycles to complete. It is suggested to generate sclk from clk with a clock division ratio of 4.
The Nixel 512 chip supports clk frequencies up to 160 MHz, providing ADC sampling rates up to 12-bit resolution at 32 kHz sampling rate. In this case, ADC sampling time will be 31.25 μs, and the serial data stream for full resolution (64 nixels or 128 electrodes per panel) will only take 6.4 μs, which is less than 21% of the available ADC sampling time. In cases where 10-bit ADC resolution will be enough, a 40 MHz clk will be sufficient for the same 32 kHz ADC sampling. In this 32 kHz 10-bit ADC mode, serial data can be transmitted in 25.6 μs, which will correspond to about 82% of the available ADC sampling time. At clock frequencies less than ~33MHz, it will not be possible to maintain 32kHZ ADC sampling rate without decreasing the ADC resolution below 10-bit. If lower resolution is not an option, then the ADC sampling rate can be reduced to 16kHz or below to allow enough clock cycles for the single-slope type ADCs to perform ADC conversion. For example, 16 kHz ADC sampling with 10-bit resolution will be possible with clock frequencies just above 17 MHz.
Summary table
| Power supplies and returns (grounds) | Analog power | vdda_bg | Bias generator supply | 2.5 V | |
| vdda_lna | Nixel LNA supply | 2.5 V | |||
| vdda_cmp | Nixel comparator supply | 2.5 V | |||
| Analog ground | vssa_bg | Bias generator ground | 0.0 V | ||
| vssa_lna | Nixel LNA ground | 0.0 V | |||
| vssa_cmp | Nixel comparator ground | 0.0 V | |||
| sub | Substrate, ground | 0.0 V | |||
| Digital power | dvdd2p5 | Level shifter supply | 2.5 V | ||
| dvdd | Core and I/O supply | 1.2 V | |||
| Digital ground | dvss | All digital block, ground | 0.0 V | ||
| Power dissipation | 32 KHz sampling 12-bit ADC resolution 160 MHz clk | Analog | ≤ 22mW | ||
| Digital | ≤ 8mW | ||||
| Total | ≤ 30mW | ||||
| Power dissipation can be reduced to 15 mW at 16 kHz sampling with 10-bit ADC resolution with a 20 MHz clk | |||||
| Digital I/Os | 1.2V CMOS I/Os | Output impedance (fixed drive strength) ≤ 100 W | |||
| Outputs | Capacitive only loads | ||||
| High-speed data / test | SPI output | ||||
| ≤ 10 pF, up to 160 MHz | ≤ 40 pF, up to 40 MHz | ||||
| System inputs | rstb: active low reset input | ||||
| clk: system clock, 50% duty cycle, 160 MHz (Rise-time = fall-time ≤ 25% of clk period, 1.56ns) | |||||
| 4-wire SPI | csn: active low chip select, generated at falling sclk | ||||
| sdin: serial data input, generated at falling sclk | |||||
| sclk: serial clk (40 MHz, 1/4th of clk frequency)(Rise-time = fall-time ≤ 6.25 ns) | |||||
| sdout: serial data output, sampled at falling sclk (Load for sdout ≤ 40 pF) | |||||
| Serial data ports | 160 Mbps at 160 MHz system clock Load for data ports ≤ 10 pF | ||||
| Port-0 | data_ser_out<0> wclk_ser_out<0> | ||||
| Port-1 | data_ser_out<1> wclk_ser_out<1> | ||||
| Port-2 | data_ser_out<2> wclk_ser_out<2> | ||||
| Port-3 | data_ser_out<3> wclk_ser_out<3> | ||||
| Package | Flip-chip CSP with Cu bumps | 4 mm x 4 mm | |||
| Bump array / pitch | 28 x 26 | 724 Bumps (none on corners) | 140 µm | ||
| Cu bump composition | 40 µm Cu + 20 µm SnAg | ||||
| Die thickness | 12 mil (~305 µm) | ||||
Technical specifications
| Active electrodes | Active | Reference | Test | ||
| 512 | 8 | 8 | |||
| Input capacitance | 6.8 pF | ||||
| Panel count | 4 panels | ||||
| One panel has 128 active electrodes, 2 reference, and 2 test electrodes | |||||
| Neural interface elements (nixels) | Selectable input configuration | ||||
| Differential or single-ended operation | |||||
| LNA + S/H + Comparator | |||||
| Sample-and-hold (S/H) | Ping-pong architecture, with dual analog memory | ||||
| Comparator | In-nixel digitization with comparator | ||||
| Analog front-end of single-slope ADC | |||||
| ADC parameters | Single-slope-ADC, distributed architecture | ||||
| User selectable resolution, 12–16-bit in resolution, ≤ 32 kHz in sampling | |||||
| ADC Mode-0: Low resolution, high sample rate | 10-bit @ 32 kHz sampling, 40 MHz clk | ||||
| ADC Mode-1: High resolution, mid sample rate | 12-bit @ 16 kHz sampling, 80 MHz clk | ||||
| ADC Mode-2: High resolution, high sample rate | 12-bit @ 32 kHz sampling, 160 MHz clk | ||||
| ADC Mode-3: Very high resolution low sample rate | 14-bit @ 8 kHz sampling, 160 MHz clk | ||||
| ADC Mode-4: Ultra high resolution very low sample rate | 16-bit @ 2kHz sampling, 160 MHz clk | ||||
| Active electrodes | Configurations | Total | Spike | LFP | |
| Differential, all for spike | 512 | 480 | 32 | ||
| Diff. spike, single ended LFP | 496 | 480 | 16 | ||
| Single ended spike, single ended LFP | 256 | 240 | 16 | ||
| Reference electrodes | 2 external reference electrodes / panel | Spike and LFP nixels have separate external reference electrode connections | |||
| 2 external reference electrodes / chip | |||||
| 1 external reference electrodes / panel | Single external reference electrode | ||||
| Programmable internal reference | Using internal DACs as reference | ||||
| Analog drive | On-chip bias generation | Band-gap based programmable bias generation using voltage and current mode DACs | |||
| 12-bit v-DACs (references and test signals) | |||||
| 7-bit i-DACs | |||||
| Ramp generation for ADC | Programmable ramp generation for ADC with variable slope and reset parameters | ||||
| Digital drive | Flexible and programmable operation of the chip | Programmable static circuit configuration of analog and digital circuits in terms of connectivity | |||
| Programmable timing generation for nixels and ADCs to adjust resolution and conversion time | |||||
| Command based operation of the chip | |||||
| Address based programming over SPI | |||||
| Programming interface | Serial | 4-wire SPI | |||
| 32-bit SPI Words | |||||
| 8-bit command, 8-bit address, 16-bit data | |||||
| “48 sclk cyles” per SPI operation | |||||
| Test outputs | Analog | 2 Analog voltage test output pads to monitor on-chip generated biases and reference voltages using a pseudo-differential way | |||
| Voltage test outputs can be used to overwrite internally generated biases and references, including the global routing resources for reference and test electrodes used in the Nixel Array | |||||
| 1 test current output to monitor on-chip generated reference and i-DAC output current | |||||
| Digital | 3-bit digital test outputs to monitor internal digital signals can also be configured to work as general-purpose output pins controlled over SPI | ||||