The Nixel512 contains 101 writable (RAM) registers. Below are the descriptions and default values of all of the registers.

AnaDrive

ADR	REG NAME	REG INFO / NET NAME	DEF (HEX)	15	14	12	11	10	9	8	7	6	5	4	3	2	1	0
0	d_bgvref[7:0]	BandGap and Vref Settings	0000	‎							test_bg[2:0]			start_bg	pd_bg	pd_ota_vref	pull_down_drv_vref	pull_up_drv_vref
1	d_irefdac[15:0]	Iref Settings	0840	pd_iref	d_iref[7:0]							d_idac[6:0]
2	d_vdac0[12:0]	vdac0_vcm_lna	0908	‎		pd_vdac_0	vdac_0[11:0]
3	d_vdac1[12:0]	vdac1_vncas_lna	0908	‎		pd_vdac_1	vdac_1[11:0]
4	d_vdac2[12:0]	vdac2_vpcas_lna	0908	‎		pd_vdac_2	vdac_2[11:0]
5	d_vdac3[12:0]	vdac3_vcm_pre	0908	‎		pd_vdac_3	vdac_2[11:0]
6	d_vdac4[12:0]	vdac4_vref_int	073A	‎		pd_vdac_4	vdac_4[11:0]
7	d_vdac5[12:0]	dac5_vref_ramp	0908	‎		pd_vdac_5	vdac_5[11:0]
8	d_vdac6[12:0]	vdac6_vimp	0172	‎		pd_vdac_6	vdac_6[11:0]
9	d_vdac7[12:0]	vdac7_vtest	0172	‎		pd_vdac_7	vdac_7[11:0]
10	d_vdac8[12:0]	vdac8_vref_test	0172	‎		pd_vdac_8	vdac_8[11:0]
11	d_vdac9[12:0]	vdac9_vncas	0908	‎		pd_vdac_9	vdac_9[11:0]
12	d_vdac10[12:0]	vdac10_vpcas	0908	‎		pd_vdac_10	vdac_10[11:0]
13	d_idac0[7:0]	idac0_vnbias_lna	0010	‎							pd_idac_0	idac_0[6:0]
14	d_idac1[7:0]	idac1_vpbias_pre	0010	‎							pd_idac_1	idac_1[6:0]
15	d_idac2[7:0]	idac2_vnbias_d2s	0010	‎							pd_idac_2	idac_2[6:0]
16	d_idac3[7:0]	idac3_i_int	0020	‎							pd_idac_3	idac_3[6:0]
17	d_idac4[7:0]	idac4_ipbias_int	0020	‎							pd_idac_4	idac_4[6:0]
18	d_idac5[7:0]	idac5_ipbias_ramp	0020	‎							pd_idac_5	idac_5[6:0]
19	d_idac6[7:0]	idac6_inbias_vdac0	0050	‎							pd_idac_6	idac_6[6:0]
20	d_idac7[7:0]	idac7_inbias_vdac1_2	0050	‎							pd_idac_7	idac_7[6:0]
21	d_idac8[7:0]	idac8_inbias_vdac3	0050	‎							pd_idac_8	idac_8[6:0]
22	d_idac9[7:0]	idac9_inbias_vdac4	0050	‎							pd_idac_9	idac_9[6:0]
23	d_idac10[7:0]	idac10_inbias_vdac5	0050	‎							pd_idac_10	idac_10[6:0]
24	d_idac11[7:0]	idac11_inbias_vdac6_7_8	0050	‎							pd_idac_11	idac_11[6:0]
25	d_test[10:0]	Analog Test MUX Settings	0000	‎				enable_itest	sel_itest	enable_vtest	sel_vtest1[3:0]				sel_vtest0[3:0]
26	d_ramp[5:0]	RampGen Settings	0006	‎									ramp_test_enable	ramp_pd	ramp_scap[3:0]
27	d_eltest[15:0]	Electrode MUX Settings: Test Electrodes	0000	eltest_3[3:0]			eltest_2[3:0]				eltest_1[3:0]				eltest_0[3:0]
28	d_elref[15:0]	Electrode MUX Settings: Ref Electrodes	CCCC	elref_3[3:0]			elref_2[3:0]				elref_1[3:0]				elref_0[3:0]
29	d_elbus[15:0]	Electrode MUX Settings: Test Read Busses	0000	elbus_3[3:0]			elbus_2[3:0]				elbus_1[3:0]				elbus_0[3:0]
30	d_elimp[7:0]	Electrode MUX Settings: Impedance Read Busses	0000	‎							elimp_3[1:0]		elimp_2[1:0]		elimp_1[1:0]		elimp_0[1:0]

Nixel

ADR	REG NAME	REG INFO / NET NAME	DEF (HEX)	15	13	11	10	9	7	5	3	1
31	s_sw[15:0]	Nixel-BOT Input Switches	1080	spe_BOT[4:0]			sne_BOT[4:0]			simp_BOT[5:0]
32	s_sw[31:16]	Nixel-TOP Input Switches	1080	spe_TOP[4:0]			sne_TOP[4:0]			simp_TOP[5:0]
33	s_lna[15:0]	LNA-BOT HP + LP Filter Corner Selection	0010	lp_BOT[3:0]		hp_BOT[7:0]					gain_cap_BOT[3:0]
34	s_lna[31:16]	LNA-TOP HP + LP Filter Corner Selection	0010	lp_TOP[3:0]		hp_TOP[7:0]					gain_cap_TOP[3:0]
35	pd[15:0]	Power-Down for 16 Nixels, Start Index = 0	FFFF	pd[15:0]
36	pd[31:16]	Power-Down for 16 Nixels, Start Index = 16	FFFF	pd[31:16]
37	pd[47:32]	Power-Down for 16 Nixels, Start Index = 32	FFFF	pd[47:32]
38	pd[63:48]	Power-Down for 16 Nixels, Start Index = 48	FFFF	pd[63:48]
39	pd[79:64]	Power-Down for 16 Nixels, Start Index = 64	FFFF	pd[79:64]
40	pd[95:80]	Power-Down for 16 Nixels, Start Index = 80	FFFF	pd[95:80]
41	pd[111:96]	Power-Down for 16 Nixels, Start Index = 96	FFFF	pd[111:96]
42	pd[127:112]	Power-Down for 16 Nixels, Start Index = 112	FFFF	pd[127:112]
43	pd[143:128]	Power-Down for 16 Nixels, Start Index = 128	FFFF	pd[143:128]
44	pd[159:144]	Power-Down for 16 Nixels, Start Index = 144	FFFF	pd[159:144]
45	pd[175:160]	Power-Down for 16 Nixels, Start Index = 160	FFFF	pd[175:160]
46	pd[191:176]	Power-Down for 16 Nixels, Start Index = 176	FFFF	pd[191:176]
47	pd[207:192]	Power-Down for 16 Nixels, Start Index = 192	FFFF	pd[207:192]
48	pd[223:208]	Power-Down for 16 Nixels, Start Index = 208	FFFF	pd[223:208]
49	pd[239:224]	Power-Down for 16 Nixels, Start Index = 224	FFFF	pd[239:224]
50	pd[255:240]	Power-Down for 16 Nixels, Start Index = 240	FFFF	pd[255:240]
51	s_cmp[15:0]	Digital Output Mux Select for Nixel	AAAA	s_cmp_3_TOP[1:0]	s_cmp_3_BOT[1:0]	s_cmp_2_TOP[1:0]		s_cmp_2_BOT[1:0]	s_cmp_1_TOP[1:0]	s_cmp_1_BOT[1:0]	s_cmp_0_TOP[1:0]	s_cmp_0_BOT[1:0]

ADC

ADR	REG NAME	REG INFO / NET NAME	DEF (HEX)	15	7	3
52	N_start_adc[15:0]	Start Value for ADC Counter, glb setting	00FA	N_start_ADC[15:0]
53	N_stop_adc[15:0]	Stop Value for ADC Counters, glb setting	1324	N_stop_ADC[15:0]
54	{gray_adc[3:0], rstb_adc[3:0]}	Gray/Bin Count Modes + ADC_Reset_Bar	0000	‎	gray_adc[3:0]	rstb_adc[3:0]

DigCont

ADR	REG NAME	REG INFO / NET NAME	DEF (HEX)	15	14	11	10	9	8	7	6	5	4	3	2	1	0
55	sel_panel[7:0]	Panel Select for Dig. Test Outs and Ramp Controls	0011	‎						sel_panel_test_outputs[3:0]				sel_panel_ramp_control[3:0]
56	sel_test[14:0]	Select Active Dig. Test Outputs, 4-bit x 3 Mux Select Signals, global for all Panels	7000	‎	enable_digtest_out[2:0]	select_digtest_out_2[3:0]				select_digtest_out_1[3:0]				select_digtest_out_0[3:0]
57	enable_oe_ser[11:0]	Enable Serializer for Panels, ON Signal for Data /Wclk for each Panel	0FFF	‎		enable_serializer[3:0]				enable_wclk[3]	enable_data[3]	enable_wclk[2]	enable_data[2]	enable_wclk[1]	enable_data[1]	enable_wclk[0]	enable_data[0]
58	enable_mode_select_hs[15:0]	Enable Horizontal_Scanner, Mode Select Horizontal_Scanner	F000	enable_hs[3:0]		test_mode_select_hs_3[3:0]			test_mode_select_hs_2[3:0]			test_mode_select_hs_1[3:0]			test_mode_select_hs_0[3:0]
59	chip_port_id_hs[15:0]	8-bit Chip ID (default h00), and 4-Port IDs for Panels. 8-bit Port IDs defaults are: 11, 10, 01, 00 (default hE4)	00E4	chip_id[7:0]						port_id_3[1:0]		port_id_2[1:0]		port_id_1[1:0]		port_id_0[1:0]
60	spi_scan_window_size[15:0]	Windowing Register for Panel-0: 8-bit Column Count, 8-bit Column Start	4000	column_count_0[7:0]						column_start_0[7:0]
61	spi_scan_window_size[31:16]	Windowing Register for Panel-1: 8-bit Column Count, 8-bit Column Start	4000	column_count_1[7:0]						column_start_1[7:0]
62	spi_scan_window_size[47:32]	Windowing Register for Panel-2: 8-bit Column Count, 8-bit Column Start	4000	column_count_2[7:0]						column_start_2[7:0]
63	spi_scan_window_size[63:48]	Windowing Register for Panel-3: 8-bit Column Count, 8-bit Column Start	4000	column_count_3[7:0]						column_start_3[7:0]
64	spi_scan_start_time[15:0]	Horizontal Scanner Start Time for Panel-0	0032	scan_start_time_0[15:0]
65	spi_scan_start_time[31:16]	Horizontal Scanner Start Time for Panel-1	0032	scan_start_time_1[15:0]
66	spi_scan_start_time[47:32]	Horizontal Scanner Start Time for Panel-2	0032	scan_start_time_2[15:0]
67	spi_scan_start_time[63:48]	Horizontal Scanner Start Time for Panel-3	0032	scan_start_time_3[15:0]
68	spi_scan_data[15:0]	SPI Scan Data: Static Test Data from SPI (for the Last MUX in Data Path, Default h2301, which is Prod ID for ASIC01	2301	spi_scan_data[15:0]
69	enable_adc_timing_limit[7:0]	Enable for ADC Timing Generators in DigCont and Enable Count Limit for ADC Counters in DigRecord	00FF	‎						enable_adc_timing[3:0]				enable_adc_count_limit[3:0]
70	dtest_mode_cmp[7:0]	8-bit Mode select for D-test Signal Generation for Nixel Comps. 3-bit per Panel.	00FF	‎						dtest_mode_cmp_3[1:0]		dtest_mode_cmp_2[1:0]		dtest_mode_cmp_1[1:0]		dtest_mode_cmp_0[1:0]
71	dtest_data_cmp[11:0]	12-bit dtest_data from SPI Register	0000	‎		dtest_data_cmp_3[2:0]			dtest_data_cmp_2[2:0]			dtest_data_cmp_1[2:0]			dtest_data_cmp_0[2:0]
72	spi_direct_control[15:0]	16-bit SPI Direct Control Register for all the on-chip generated timing signals, mainly for testing purposes	0000	enable_spi_direct_control[4:0]			start_adc_direct	enable_cmp_direct	clear_cmp_direct	dtest_cmp_direct[2:0]			phi_sh_direct[2:0]			enable_ramp_direct	rst_ramp_direct
73	spi_set_rst_ramp[15:0]	Timing: SET_RST_RAMP	0032	spi_set_rst_ramp[15:0]
74	spi_reset_rst_ramp[15:0]	Timing: RESET_RST_RAMP	012C	spi_reset_rst_ramp[15:0]
75	spi_set_enable_ramp[15:0]	Timing: SET_ENABLE_RAMP	00FA	spi_set_enable_ramp[15:0]
76	spi_reset_enable_ramp[15:0]	Timing: RESET_ENABLE_RAMP	12F2	spi_reset_enable_ramp[15:0]
77	spi_set_phi_sh[15:0]	Timing: SET_PHI_SH	00C8	spi_set_phi_sh[15:0]
78	spi_reset_phi_sh[15:0]	Timing: RESET_PHI_SH	1324	spi_reset_phi_sh[15:0]
79	spi_set_phi_rstb[15:0]	Timing: SET_PHI_RSTB	0096	spi_set_phi_rstb[15:0]
80	spi_reset_phi_rstb[15:0]	Timing: RESET_PHI_RSTB	1356	spi_reset_phi_rstb[15:0]
81	spi_set_dtest_cmp[15:0]	Timing: SET_DTEST_CMP	0096	spi_set_dtest_cmp[15:0]
82	spi_reset_dtest_cmp[15:0]	Timing: RESET_DTEST_CMP	00C8	spi_reset_dtest_cmp[15:0]
83	spi_set_clear_cmp[15:0]	Timing: SET_CLEAR_CMP	0032	spi_set_clear_cmp[15:0]
84	spi_reset_clear_cmp[15:0]	Timing: RESET_CLEAR_CMP	0064	spi_reset_clear_cmp[15:0]
85	spi_set_enable_cmp[15:0]	Timing: SET_ENABLE_CMP	015E	spi_set_enable_cmp[15:0]
86	spi_reset_enable_cmp[15:0]	Timing: RESET_ENABLE_CMP	12C0	spi_reset_enable_cmp[15:0]
87	spi_set_start_adc[15:0]	Timing: SET_START_ADC	00FA	spi_set_start_adc[15:0]
88	spi_reset_start_adc[15:0]	Timing: RESET_START_ADC	12F2	spi_reset_start_adc[15:0]
89	spi_line_time[15:0]	LINE TIME REGISTER for Panel-0. It is suggested to have same LINE time for all Panels.	1388	spi_line_time[15:0]
90	spi_line_time[31:16]	LINE TIME REGISTER for Panel-1. It is suggested to have same LINE time for all Panels.	1388	spi_line_time[31:16]
91	spi_line_time[47:32]	LINE TIME REGISTER for Panel-2. It is suggested to have same LINE time for all Panels.	1388	spi_line_time[47:32]
92	spi_line_time[63:48]	LINE TIME REGISTER for Panel-3. It is suggested to have same LINE time for all Panels.	1388	spi_line_time[63:48]
93	{enable_line_time[3:0], auto_line_time[3:0]}	8-bit ENABLE_TRIGGER_LINE_TIME_REGISTER: Enabled all Panales by Default, Expects SPI AUTO Trigger	00F0	‎						enable_line_time[3:0]				auto_line_time[3:0]
94	{enable_rstb_retime[4:0], enable_signal_retime[3:0]}	9-bit ENABLE_RSTB_SIGNAL_REGISTER. All RSTB and SIGNAL Retime functions are ON by Default.	01FF	‎					enable_rstb_retime[4:0]					enable_signal_retime[3:0]
95	spi_gpout[2:0]	3-bit SPI_GPOUT REGISTER. Use Reg#55 to configure to use SPI_GPO UT for digtest_out[2:0]	0000	‎											spi_gpout[2:0]

Unused

ADR	REG NAME	REG INFO / NET NAME	15
96	unused_register0[15:0]	Can be used for SPI R/W Testing	unused_register0[15:0]
97	unused_register1[15:0]	Can be used for SPI R/W Testing	unused_register1[15:0]
98	unused_register2[15:0]	Can be used for SPI R/W Testing	unused_register2[15:0]
99	unused_register3[15:0]	Can be used for SPI R/W Testing	unused_register3[15:0]
100	unused_register4[15:0]	Can be used for SPI R/W Testing	unused_register4[15:0]
101	unused_register5[15:0]	Can be used for SPI R/W Testing	unused_register5[15:0]

On-Chip Registers

AnaDrive

Nixel

ADC

DigCont

Unused