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The Nixel 512™ chip measures 4 mm x 4 mm x 0.3 mm and uses chip scale packaging with Cu bumps. The 2D bump array counts 28 rows and 26 columns with 724 total bumps (no bumps on corners) and a uniform bump pitch of 140 µm.

Bump Locations

Rows	Col.	Bump Name	X (um)	Y0 (um)	Y1 (um)	I/O Type	Explanation	Value	Note
A & B	1	sub	240	100	240	Analog power/ ground	Substrate	0.0 V	-
	2	vssa_bg	380				Ground / analog / bandgap	0.0 V	-
	3	vdda_bg	520				Supply / analog / bandgap	2.5 V	1.8–2.8 V adjustable
	4	vdda_lna	660				Supply / analog / LNA	2.5 V	-
	5	vssa_lna	800				Ground / analog / LNA	0.0 V	-
	6	vssa_cmp	940				Ground /analog / comparator	0.0 V	-
	7	vdda_cmp	1080				Supply / analog / comparator	2.5 V	-
	8	dvdd2p5	1220				Supply / 2.5 V digital Blocks	2.5 V	-
	9	dvdd	1360				Supply / digital / core + IOs	1.2 V	-
	10	dvss	1500				Ground / digital / core + IOs	0.0 V	-
	11	sub	1640				Substrate	0.0 V	-
	12	vdda_lna	1780				Supply / analog / LNA	2.5 V	-
	13	vssa_lna	1920				Ground / analog / LNA	0.0 V	-
	14	vssa_cmp	2060				Ground /analog / comparator	0.0 V	-
	15	vdda_cmp	2200				Supply / analog / comparator	2.5 V	-
	16	dvdd2p5	2340				Supply / 2.5V digital blocks	2.5 V	-
	17	dvdd	2480				Supply / digital / core + IOs	1.2 V	-
	18	dvss	2620				Ground / digital / core + IOs	0.0 V	-
	19	sub	2760				Substrate	0.0 V	-
	20	vdda_lna	2900				Supply / analog / LNA	2.5 V	-
	21	vssa_lna	3040				Ground / analog / LNA	0.0 V	-
	22	vssa_cmp	3180				Ground /analog / comparator	0.0 V	-
	23	vdda_cmp	3320				Supply / analog / comparator	2.5 V	-
	24	itest_out	3460				Current test pad / analog / bias generator	0–32 µA sourcing (p-mirror)	-
	25	vtest_out <0>	3600				Voltage test pad [0] / analog / bias generator	0–2.5 V vDAC outputs	-
	26	vtest_out <1>	3740				Voltage test pad [1] / analog / bias generator	0–2.5 V vDAC outputs	-
AG & AH	1	sub	240	3740	3880	Digital power / ground / IOs	Substrate	0.0 V	-
	2	dvss	380				Ground / digital / core + IOs	0.0 V	-
	3	dvdd	520				Supply / digital / core + IOs	1.2 V	-
	4	csn	660				CMOS (1.2) input: SPI chip select bar	0–1.2 V	From FPGA, at negedge sclk, 50 Ω series res
	5	sdin	800				CMOS (1.2) input: SPI data in	0–1.2V	From FPGA, at negedge sclk, 50 Ω series res
	6	sclk	940				CMOS (1.2) input: SPI clock	0–1.2 V, fsclk = 1/4 fclk, ≤ 40 MHz, 50% DTC	From FPGA, at negedge sclk, 50 Ω series res
	7	sdout	1080				CMOS (1.2) output: SPI data out	0-1.2 V	To FPGA, at posedge sclk, 50 Ω series res
	8	rstb	1220				Active low asynch. reset	0 - 1.2 V	From FPGA, 50 or 20 Ω series res
	9	clk	1360				Clock	0 - 1.2 V, fclk ≤ 160 MHz, 50% DTC	From FPGA, 50 or 20 Ω series res
	10	sub	1500				Substrate	0.0 V	-
	11	dvss	1640				Ground / digital / core + IOs	0.0 V	-
	12	dvdd	1780				Supply / digital / core + IOs	1.2 V	-
	13	data_ser<0>	1920				CMOS (1.2) output: serializer data output [0]	SDR data rate, at rising edge clk, ≤ 160 Mbps	To FPGA, 50 or 20 Ω series res
	14	wclk_ser <0>	2060				CMOS (1.2) output: serializer word clock output [0]	Frequency = 1/16 of SDR data rate	To FPGA, 50 or 20 Ω series res
	15	data_ser <1>	2200				CMOS (1.2) output: serializer data output [1]	SDR data rate, at rising edge clk, ≤ 160 Mbps	To FPGA, 50 or 20 Ω series res
	16	wclk_ser <1>	2340				CMOS (1.2) output: serializer word clock output [1]	Frequency = 1/16 of SDR data rate	To FPGA, 50 or 20 Ω series res
	17	data_ser <2>	2480				CMOS (1.2) output: serializer data output [2]	SDR data rate, at rising edge clk, ≤ 160 Mbps	To FPGA, 50 or 20 Ω series res
	18	wclk_ser <2>	2620				CMOS (1.2) output: serializer word clock output [2]	Frequency = 1/16 of SDR data rate	To FPGA, 50 or 20 Ω series res
	19	data_ser <3>	2760				CMOS (1.2) output: serializer data output [3]	SDR data rate, at rising edge clk, ≤ 160 Mbps	To FPGA, 50 or 20 Ω series res
	20	wclk_ser <3>	2900				CMOS (1.2) output: serializer word clock output [3]	Frequency = 1/16 of SDR data rate	To FPGA, 50 or 20 Ω series res
	21	sub	3040				Substrate	0.0 V	-
	22	dvss	3180				Ground / digital / core + IOs	0.0 V	-
	23	dvdd	3320				Supply / digital / Core + IOs	1.2 V	-
	24	digtest <0>	3460				CMOS (1.2) digital test output [0]	0–1.2 V	To FPGA, 50 or 20 Ω series res
	25	digtest <1>	3600				CMOS (1.2) digital test output [1]	0–1.2 V	To FPGA, 50 or 20 Ω series res
	26	digtest <2>	3740				CMOS (1.2) digital test output [2]	0–1.2 V	To FPGA, 50 or 20 Ω series res

Labeled diagram of the Nixel 512 chip showing row and column identifiers for each copper bump.

Die photo of the Nixel chip shown from the top.

Packaging

Bump Locations