The Pixel 16K™ chip is composed of four main blocks: Row Drive, Column Drive, Bias, and Digital Drive.

The Row Drive and Column Drive are each arranged in a 2D array in the center of the chip. The Row Drive is divided into the top 64 rows and the bottom 64 rows; each composed of 64 identical unit cells arranged in an 8 x 8 array with high voltage switch arrays. Column Drivers are placed on the right of the chip, composed of 128 elements arranged in 8 x 16 format. Column Drivers contain pixel-level 7-bit current mode digital-to-analog converters (i-DACs), 8-bit pixel memory, and high voltage drive circuits. The Pixel 16K chip contains large probe pads on the left side of the chip for electrical testing and small flip-chip pads for column and row drive outputs, arranged in a 2D array on top of their corresponding drivers.

The Digital Drive controls the chip and is composed of a simple digital controller with a 4-wire SPI. The SPI controls the programming values of the pixel-level i-DACs and states of output drive transistors in the Column Drive and Row Drive using soft commands.

The Pixel 16K chip operates in rolling line scanning mode; only one row of pixels is selected and biased at a given time. First, all columns and the previously selected row are disconnected. Then, the next row is connected to ground to make the corresponding columns ready for current mode drive; the current drive levels of each column come from the previously written i-DAC values. Once the columns are connected to the anodes of the LED array, the LEDs light up during the active line time period. This cycle repeats for the other rows until the entire array has been scanned.

Each pixel has an 8-bit ping-pong type memory which allows pixel memory to be written while pixel values in the previous line time are read; this optimizes the available time and improves the scanning speed. The chip supports address-based RAM-like pixel programming to improve timing efficiency when few pixels need to be updated.

The current mode drivers in the pixels have a 4x current gain at the high voltage output stage and are driven by 5 V i-DACs. The i-DACs are biased by a global bias voltage and generated by a diode connected N-MOS transistors that are biased by a constant current provided externally through the input reference current pin (iref). For an iref of 32 µA, pixel-level i-DACs will generate current outputs between 0–127 µA in 1 µA steps. Connecting the iref to a 5 V analog supply using an adjustable resistor will generate the required input reference of 32 µA locally.

The Pixel 16K chip uses an externally provided cascode voltage (vncas_col) to isolate high voltage output devices from 5 V devices from pixel-level i-DACs.This isolation is not needed for microLED applications or other applications where high voltage supply can safely be reduced to 5 V and instead, the cascode bis voltage can safely be tied to 5 V to eliminate the generation of one external bias.