The Pixel 16K™ chip runs on triple supply voltages of 11 V for the LED drivers, 5 V for analog biasing and pixel-level i-DACs, and 1.8 V for digital control. It requires two external biases, the input reference current (iref) and the cascode voltage (vncas_col).
The Pixel 16K chip uses a standard 4-wire SPI interface to program and control the chip, with active low chip select (csn), serial data input (sdin), serial clock (sclk), and serial data output (sdout). SPI interface uses 20-bit words, composed of a 4-bit command (<19:16>), an 8-bit address (<15:8>), and an 8-bit data (<7:0>) and sends the most-significant-bit (MSB) first. Since SPI operates at the rising edge of sclk, csn and sdin are applied at the falling edge of the sclk. Likewise, sdout from the SPI will be updated at the rising edge of the sclk, therefore it should be captured by the external electronics at the falling edge of sclk.
SPI timing takes 20 sclk cycles to enter the 20-bit SPI words into the input shift register of the SPI when csn is LOW. When csn is HIGH, it takes an additional 4 sclk cycles for the SPI controller to decode the SPI commands and write to the SPI registers or execute applied soft commands. Including this idle time, an SPI operation will take at least 24 sclk cycles to complete.
The Pixel 16K chip supports sclk frequencies up to 24 MHz which corresponds to a single SPI operation of 1 µs. A single line with 128 pixels will require 128 DAC writes and approximately 12 soft commands to operate output devices individually over SPI.
When the sclk frequency is 24 MHz, the line time will take 140 µs, resulting in a frame time of 17.9 ms and a frame rate of 55.8 fps with a full resolution of 128 x 128. When half of the rows are addressed, the frame rate will double and exceed 110 fps. In that case, performance may be improved by running the Pixel 16K chip at slower sclk frequencies such as 12 MHz instead of 24 MHz.
SPI commands
| No | SPI Command Name | Short Command | Hex Code |
|---|---|---|---|
| 1 | No Operation | NOP | 80000 |
| 2 | Toggle Ping-Pong | TPP | 10000 |
| 3 | Write Row Address | WRA | 20000 |
| 4 | Disconnect Rows and Columns | DRC | 30020 |
| 5 | Reset Force Column | RFC | 30021 |
| 6 | Set Force Column | SFC | 30022 |
| 7 | Reset Force Row | RFR | 30028 |
| 8 | Connect Column Drive | CCD | 3002C |
| 9 | Write Column Data | WCD | 400A0 |
Summary table
| Power supplies and returns (grounds) | Analog power | vcc_hv | Supply for high voltage LED Drivers | 11 V | |
| vhigh_col | Supply for column set level | 10 V | |||
| dvdd_5v | Supply for level shifters, i-DACs | 5 V | |||
| Analog ground | vss_hv | Ground for high voltage LED Drivers | 0.0 V | ||
| vlow_col | Ground for column reset level | 0.0 V | |||
| dvss_5v | Ground for level shifters, i-DACs | 0.0 V | |||
| sub | Substrate, ground | 0.0 V | |||
| Digital power | dvdd | Supply for core logic | 1.8 V | ||
| Digital ground | dvss | Ground for core logic | 0.0 V | ||
| Power dissipation | 24 MHz sclk, together with LEDs | Analog | ≤ 7 mW @ 10 µA drive 128 columns, 5 V vcc_hv | ||
| Digital | ≤ 3 mW from dvdd | ||||
| Total | ≤ 10mW | ||||
| Digital I/Os | 4-wire SPI | 1.8 V CMOS I/Os | |||
| csn | Active low chip select input, generated at falling sclk | ||||
| sdin | Serial data input, generated at falling sclk | ||||
| sclk | Serial clk input (≤ 24 MHz, Tr=Tf ≤ 10 ns) | ||||
| sdout | Serial data output, sampled at falling sclk, load 40 pF | ||||
| Reset | rstb | active low reset input | |||
| Package | Chip scale package | 2.7 mm x 2.4 mm | |||
| Bump type | Cu bumps | ||||
| Die thickness | 12 mil (~305 µm) | ||||
Technical specifications
| Product type | Display driver | Passive | |
| Resolution | 128 x 128 | 16K pixels | |
| Design size | 2.7 mm x 2.4 mm | 12 mil thick (~305 µm) | |
| CMOS technology | 130 nm high voltage CMOS | 11 V, 5 V, 1.8 V active devices | |
| Supply voltages | High voltage | 11 V and 10 V (LED Drive) | |
| Mid voltage | 5 V (i-DACs) | ||
| Low voltage | 1.8 V (core logic) | ||
| Column driver | Current mode drive | 128 columns, i-DAC per column | |
| DAC resolution | 7-bit | ||
| Output drive range | 0–127 µA, 1 LSB = 1 µA | ||
| Power-down | Per column | ||
| Row driver | Voltage mode drive | 128 Rows | |
| Low and high levels | |||
| Bias inputs | Current | iref, 32 µA into device | |
| Voltage | Vncas_col, 5 V | ||
| Digital I/Os | 4-wire SPI | 1.8 V CMOS | |
| csn | active low chip select, generated at falling sclk | ||
| sdin | serial data input, generated at falling sclk | ||
| sclk | serial clk (≤ 24 MHz, Tr=Tf ≤ 10ns) | ||
| sdout | serial data output, sampled at falling sclk, load 40 pF | ||
| I/O pad count | Wire bonding | 29 | Testing and probing only 60 µm x 60 µm, Pitch = 80 µm |
| Flip-chip | 128 | Column drive | |
| 16 rows x 8 columns | |||
| X-pitch = 120 µm, Y-pitch = 140 µm | |||
| 128 | Row drive | ||
| 16 rows x 8 columns | |||
| X-Pitch = 120 µm, Y-Pitch = 140 µm | |||