The Pixel A2K™ chip is composed of three main blocks: Column Drive, Row Drive, and Digital Drive.

The Column Drivers are arranged in a 2 x 32 array where each unit cell in the Column Drive circuit has a 1-bit voltage mode digital analog converter (v-DAC) and column drive logic with level shifters. The v-DACs in the Column Drive circuits use externally provided high- and low-voltage references controlled by a 1-bit column ON/OFF setting stored in the column memory of the Digital Drive block to provide two level voltage drive for the active microLED arrays. The column drive logic controls the reset and voltage drive phases of the active microLED arrays. Column drivers are placed on the right of the chip with 64 driver outputs arranged in two columns using small output pads designed for flip-chip assembly.

The Row Drivers are placed at the top and bottom of the chip, with 16 small pads on each side. They contain row drive logic, level shifters, and 5 V CMOS drivers to control the row select transistor in the pixels of active microLED arrays. The row drive logic circuit provides a gating function using the outputs of the 32-bit row select shift register and externally applied global row timing signal. This gating function assures the write operation for analog voltages to active pixels do not overlap.

The Digital Drive controls the chip and is composed of a simple digital controller with a 4-wire SPI. The SPI uses an external global row timing signal for non-overlapping write operations of the active microLED arrays, provides soft timing commands, and holds 64-bit column memory information for the rolling line scanning method. The analog data for the pixel write operation is provided by the voltage mode column drivers implemented using 1-bit v-DACs. The row-select signal required for the active pixels are provided by the row drivers implemented with 5 V CMOS logic. The row drivers are controlled by 32-bit shift row select shift registers integrated in the Digital Drive circuit. There are two copies of the 32-bit row shift registers to select even and odd rows of the active pixel array. This allows proper timing closure in the chip and allows rolling line scanning updates in both progressive mode where rows are addressed sequentially, or in interlaced mode where even and odd rows are addressed in successive frames.

The row shift registers are operated at the falling edge of the csn signal and controlled by the soft commands captured at the rising edge of csn. Pixel values are cleared at the beginning of each write cycle to prevent any coupling between old and new pixel values. This is achieved by forcing the Column Driver outputs to a low voltage level defined by the OFF state of the pixels; which also helps clear the parasitic capacitors of the Column Drive nets and prepares the active pixels for a hard voltage mode reset before analog write operation.

The Pixel A2K chip uses a single external timing signal celled row to generate non-overlapping row-select signals for the active array and to prevent any coupling between successively addressed rows of the active pixel array. The write operation is started with a hard reset operation to prevent any memory effect in the pixel response. The SPI write cycle begins with the falling edge of csn signal. After some time, the row timing signal is set to HIGH, which causes the row-select signal of the selected row in the array to go HIGH and initiates the analog hard reset cycle in the voltage mode drive. During the reset cycle, csn is kept LOW to send new data to the SPI for the current row while Column Drive outputs are kept at a low reference voltage for a hard pixel reset (this will clear the analog stored voltages in the pixels). After some time, csn rises back to HIGH which causes the Column DACs to read out their most recent updated values. Once the output of the column drivers have settled, the row signal can be set to LOW to cause the row-select transistor in the active pixel to turn off and indicate the analog sampling time of the voltage outputs of the Colum Driver into the gate storage capacitances in the currently selected row of pixels.