The Pixel A2K™ chip is fabricated with CMOS processes and runs on dual supply voltages of 5 V for column and row drivers and 1.8 V for digital core. The chip uses two external reference voltages (vref_low and vref_high) for the 1-bit v-DACs of the Column Drivers. It uses a standard 4-wire SPI interface to program and control the chip, with active low chip select (csn), serial data input (sdin), serial clock (sclk), and serial data output (sdout).
The chip measures only 1.33 mm x 1.33 mm and is designed for flip-chip packaging with small pads measuring 20 μm x 10 μm and a pitch of 30 μm. It has 12 I/O large and small pads on the left for power, ground, and digital control; 16 small pads on the top for even row drivers; 16 small pads on the bottom for odd row drivers; and 64 pads for column drivers on the right arranged into two columns. Small pads are for flip-chip assembly while large pads can be used for die probing. The large pads on the left of the chip measure 60 μm x 60 μm with an 80 μm pitch.
The Pixel A2K chip uses a standard 4-wire SPI interface to program and control the chip, with active low chip select (csn), serial data input (sdin), serial clock (sclk), and serial data output (sdout). The SPI interface uses 72-bit words composed of an 8-bit command (command<71:64>) and a 64-bit data (data<63:0>), it sends the most-significant-bit (MSB) first. Since SPI operates at the rising edge of sclk, csn and sdin are applied at the falling edge of the sclk. Likewise, sdout from the SPI will be updated at the rising edge of the sclk, therefore it should be captured by the external electronics at the falling edge of sclk.
SPI timing takes 72 sclk cycles to enter the 72-bit SPI words into the input shift register of the SPI when csn is LOW. When csn is HIGH, it takes an additional 8 sclk cycles for the SPI controller to decode the SPI commands and write to the SPI registers or execute applied soft commands. Including this idle time, an SPI operation will take at least 80 sclk cycles to complete.
The SPI write operation is practically instantaneous as it can be completed in 5 μs at a clock frequency of 16 MHz or a frame update time of 160 μs. The Pixel A2K chip can support frame rates from 2500 fps down to 25 fps, with corresponding frame times ranging from 0.4 ms up to 40 ms. For example, the ratio of available exposure time to total frame time will be 99.6% of a practical frame rate of 25 fps and only 96% when the frame rate is set to 250 fps.
Summary Table
| Power supplies and returns (grounds) | High voltage power | dvdd_5v | Supply for Row, Column Drivers | 5.0 V | |
| Low voltage power | dvdd | Supply for digital core | 1.8 V | ||
| Ground | dvss | Ground return for supplies | 0.0 V | ||
| sub | Substrate | 0.0 V | |||
| Power dissipation | 60 fps, 16 MHz sclk | Analog | ≤ 0.30 mW, 100 pF column load, 64 columns, 5 V operation | ||
| Digital | ≤ 0.05 mW | ||||
| Total | ≤ 0.35 mW | ||||
| Analog inputs | vref_high | High reference voltage for v-DACs, 2.5 V ≤ vref_high ≤ 5 V | |||
| vref_low | Low reference voltage for v-DACs, 0 V ≤ vref_low ≤ 2.5 V | ||||
| Digital I/Os | 4-wire SPI | 1.8V CMOS I/Os | |||
| csn | Active low chip select, generated at falling sclk | ||||
| sdin | Serial data input, generated at falling sclk | ||||
| sclk | Serial clk (≤ 16 MHz, Tr=Tf ≤ 15 ns) | ||||
| sdout | Serial data output, sampled at falling sclk, load 20 pF | ||||
| External row timing | row | Provides global row timing | |||
| Pads | Row Drivers | Top | 16 small pads | Even rows | For flip-chip 20 µm x 10 µm with 30 µm pitch |
| Bot | 16 small pads | Odd rows | |||
| Column Drivers | Left | 64 small pads | Two columns | ||
| CMOS I/Os | Right | 12 small pads | 12 x (2x3) | ||
| 12 large pads | 12 x 1 | For probing 60 µm x 60 µm with 80 µm pitch | |||
| Package | Chip-scale-package | Suitable for flip-chip bonding (by default bare dies w/o bumps) | |||
Technical Specifications
| Product type | Display driver | Active | |
| Resolution | 64 x 32 | 2K pixels | |
| Design size | 1.33 mm x 1.33 mm | 12 mil thick (~305 µm) | |
| CMOS technology | 180 nm high voltage CMOS | 5 V and 1.8 V active devices | |
| Supply voltages | High voltage | 5.0 V, row and column drivers | |
| Low voltage | 1.8 V (core logic) | ||
| Column driver | Voltage mode driver | 64 columns, v-DAC per column | |
| DAC resolution | 1-bit | ||
| High / low levels | Externally provided by vref_low and vref_low | ||
| Power-down | Per column | ||
| Row driver | Voltage mode drive | 32 rows, 5 V CMOS | |
| Odd and even | |||
| Reference inputs | Voltage | vref_high, high level for 1-bit v-DACs, 2.5 V ≤ vref_high ≤ 5.0 V | |
| vref_low, low level for 1-bit v-DACs, 0 V ≤ vref_low ≤ 2.5 V | |||
| Digital I/Os | 4-wire SPI | 1.8 V CMOS | |
| csn | Active low chip select, generated at falling sclk | ||
| sdin | Serial data input, generated at falling sclk | ||
| sclk | Serial clk (≤ 16 MHz, Tr=Tf ≤ 15 ns) | ||
| sdout | Serial data output, sampled at falling sclk, load 20 pF | ||
| I/O Pad Count | Probing | 12 | Power and I/Os for probing only 60 µm x 60 µm, pitch = 80 µm |
| Flip-chip | Power and I/Os for flip-chip. 3 x 2 small pads per signal. Pad size = 20 µm x 10 µm, pitch = 30 µm | ||
| 64 | Column Drive | ||
| 32 rows x 2 columns | |||
| Pad size = 20 µm x 10 µm, pitch = 30 µm | |||
| 32 | Row Drive | ||
| 16 rows top and bottom | |||
| Pad size = 20 µm x 10 µm, pitch = 30 µm | |||
| Package | Chip-scale package | Suitable for flip-chip packaging | |
| Die size | 1.33 mm x 1.33 mm | ||
| Die thickness | 12 mil (~305 µm) | ||