Loading...

Overview

Process overview

Design rules

Changelog

Two Layer Thin Film Electronics Design Rules

There are 11 masks associated with one of the wafer levels outlined below.

Material layer Lithography mask name Field type Lithography purpose
SubstrateMESA light Defines the geometry for p-type higher conductive GaN.
SubstrateDEEP ETCH light Defines the geometry for individual LEDs.
SubstrateCONTACT dark Defines the geometry for the LED contact. Metal is 3 nm Cr, 100 nm Al, 75 nm Ti, and 75 nm Pt.
Polyimide 1VIA1 dark Defines through holes from the polyimide 1 layer to the LED contacts as well as the final geometry to be released.
Polyimide 1METAL1 dark Defines the geometry of metal for electrical connections. Metal is 20 nm Ti, 20 nm Pt, 160 nm Au, 40 nm Pt, and 20 nm Ti.
Polyimide 2VIA2 dark Defines through holes from the polyimide layer 2 to the polyimide layer 1 as well as the final geometry to be released.
Polyimide 2METAL2 dark Defines the geometry of metal for electrical connections. Metal is 20 nm Ti, 20 nm Pt, 160 nm Au, 40 nm Pt, and 20 nm Ti.
Polyimide 3VIA3 dark Defines through holes from the polyimide layer 3 to the polyimide layer 2 as well as the final geometry to be released.
Polyimide 3TOPMETAL light Defines the geometry of metal for electrical connections. Metal is 20 nm Ti and 100 nm Pt.
Polyimide 3PLATING dark Defines the geometry of electroplating metal. Electroplated metal is 11 µm Cu and 8 µm Sn.
Polyimide 3ELECTRODES dark Defines the geometry for TiN electrodes.

The below table summarizes Science’s naming conventions and design limitations for each masking level.

Mnemonic mask nameGDS mask numberMin. feature width (µm)Min. space (µm)
MESA10 40 100
ISOLATE20 60 90
CONTACT30 8 140
VIA140 35 105
METAL150 5 5
VIA260 6 9
METAL270 5 5
VIA380 16 40
METAL390 50 30
PLATING100 50 30
ELECTRODES110 20 130
SHADOW MASK111 12000 5000