Docs - Science

The Two Layer TFE process uses three masks and a variety of masking levels to pattern and etch the wafer layers. The process uses double-side polished, fused silica wafers that measure 6 in and 500 µm thick. Diagrams below are not shown to scale, sizes have been exaggerated for educational purposes.

Color legend for diagrams below

	Step 1 A 5 µm layer of polyimide is deposited onto the sapphire substrate via spin coating. The wafer is then cured in nitrogen gas for 30 minutes at 350°C.

A layer of polyimide is shown atop a layer of substrate.

Step 1

A 5 µm layer of polyimide is deposited onto the sapphire substrate via spin coating. The wafer is then cured in nitrogen gas for 30 minutes at 350°C.

	Step 2 The polyimide 1 layer is patterned with the dark field VIA1 mask and a via is etched to the negative terminal of the LED.

Two resist layers are shown atop a layer of polyimide which is shown atop a layer of substrate.

Step 2

The polyimide 1 layer is patterned with the dark field VIA1 mask and a via is etched to the negative terminal of the LED.

	Step 3 A 240 nm layer of pad metal is deposited on top of the wafer in the pattern of the dark field METAL1 mask—this is composed of 20 nm Ti, 20 nm Pt, 160 nm Au, 20 nm Pt, and 20 nm Ti.

A polyimide wafer is shown with two patterned layers of resist atop it.

Step 3

A 240 nm layer of pad metal is deposited on top of the wafer in the pattern of the dark field METAL1 mask—this is composed of 20 nm Ti, 20 nm Pt, 160 nm Au, 20 nm Pt, and 20 nm Ti.

	Step 4 The resist is removed with a chemical strip.

A stack of metal is shown sitting across a wafer with patterned resist.

Step 4

The resist is removed with a chemical strip.

	Step 5 The polyimide 2 layer is applied to the top of the wafer.

A pattern of metal is shown sitting alone on a layer of polyimide.

Step 5

The polyimide 2 layer is applied to the top of the wafer.

	Step 6 A layer of resist is patterned with the dark field VIA2 mask.

A pattern of metal is shown sandwiched between two layers of polyimide.

Step 6

A layer of resist is patterned with the dark field VIA2 mask.

	Step 7 The polyimide 1 and 2 layers are etched to the positive terminal of the LED.

A pattern of resist is shown atop two polyimide layers that are sandwiching a layer of metal in an identical pattern.

Step 7

The polyimide 1 and 2 layers are etched to the positive terminal of the LED.

	Step 8 A 240 nm layer of pad metal is deposited on top of the wafer and patterned to the dark field METAL2 mask—this is composed of 20 nm Ti, 20 nm Pt, 160 nm Au, 20 nm Pt, and 20 nm Ti.

A thin layer of metal is shown atop a wafer of polyimide and resist.

Step 8

A 240 nm layer of pad metal is deposited on top of the wafer and patterned to the dark field METAL2 mask—this is composed of 20 nm Ti, 20 nm Pt, 160 nm Au, 20 nm Pt, and 20 nm Ti.

	Step 9 The resist is removed with a chemical strip.

A thin layer of metal is shown in a reverse pattern to the buried metal layer sandwiched between two polyimide layers.

Step 9

The resist is removed with a chemical strip.

	Step 10 The polyimide 3 layer is applied to the top of the wafer.

The previously buried metal layer is shown exposed after the second polyimide layer is etched away in an identical pattern.

Step 10

The polyimide 3 layer is applied to the top of the wafer.

	Step 11 A layer of resist is patterned with the dark field VIA2 mask.

The thin metal layer on top of the wafer has disappeared and action lines draw attention to the buried metal layer.

Step 11

A layer of resist is patterned with the dark field VIA2 mask.

	Step 12 The polyimide 3 layer is etched to the metal 2 layer.

Two new layers of resist are added.

Step 12

The polyimide 3 layer is etched to the metal 2 layer.

	Step 13 The resist is removed with a chemical strip.

The resist layers are shown with an etch pattern identical to the electrode sites.

Step 13

The resist is removed with a chemical strip.

	Step 14 A layer of resist is patterned with the dark field VIA3 mask.

A second layer of metal is shown deposited across the top of the wafer and into the etch holes.

Step 14

A layer of resist is patterned with the dark field VIA3 mask.

	Step 15 A 120 nm layer of top metal is deposited on top of the wafer and patterned to the light field TOPMETAL mask—this is composed of 20 nm Ti and 100 nm Pt.

The resist layers are removed, leaving just two metal layers enclosed on three sides by polyimide atop the substrate layer.

Step 15

A 120 nm layer of top metal is deposited on top of the wafer and patterned to the light field TOPMETAL mask—this is composed of 20 nm Ti and 100 nm Pt.

	Step 16 The resist is removed with a chemical strip.