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Overview

Process overview

Design rules

Design standards

Changelog

Poly Design Rules

There are eight primary masks that are each associated with one of the wafer levels outlined below. The nitride layer has no mask that directly patterns it. The HOLE0, HOLE1, HOLE2, and HOLEM are extra, special-use masking levels that should only be used to define geometries of etch holes—these provide a simpler method of extracting holes from their associated light field masks.

Material layer Thickness (µm) Lithography mask name Field type Lithography purpose
Nitride0.6 N/A N/A N/A
Polysilicon 00.5 POLY0 light Defines the structures to keep in the polysilicon 0 layer.
Polysilicon 00.5 HOLE0 dark Defines the holes to etch in the polysilicon 0 layer.
Polysilicon 12.0 POLY1 light Defines the structures to keep in the polysilicon 1 layer.
Polysilicon 12.0 HOLE1 dark Defines the holes to etch in the polysilicon 1 layer.
Polysilicon 21.5 POLY2 light Defines the structures to keep in the polysilicon 2 layer.
Polysilicon 21.5 HOLE2 dark Defines the holes to etch in the polysilicon 2 layer.
Metal0.52 METAL light Defines the structures to keep in the metal layer.
Metal0.52 HOLEM dark Defines the holes to etch in the metal layer.
Oxide 12.0 ANCHOR1 dark Defines through-holes from the polysilicon 1 layer to either the nitride or polysilicon 0 layers.
Oxide 12.0 DIMPLE dark Defines dimples/bushings for the polysilicon layer 1.
Oxide 20.75 ANCHOR2 dark Defines through-holes from the polysilicon 2 layer to either the nitride or polysilicon 0 layers.
Oxide 20.75 POLY1_POLY2_VIA dark Defines through-holes between the polysilicon 1 and polysilicon 2 layers.

The below table summarizes Science’s naming conventions and design limitations for each masking level.

Mneumonic mask nameGDS mask numberNominal feature length (µm)Min. feature length (µm)Feature tolerance (µm)Min. space (µm)
POLY0 13 3.0 2.0 ± 0.20 2.0
DIMPLE 50 3.0 2.0 ± 0.20 3.0
ANCHOR1 43 3.0 3.0 ± 0.30 2.0
POLY1 45 3.0 2.0 ± 0.25 2.0 (for orthogonal) 2.5 (for non-orthogonal)
POLY1_POLY2_VIA 47 3.0 2.0 ± 0.25 2.0
ANCHOR2 52 3.0 3.0 ± 0.25 2.0
POLY2 49 3.0 2.0 ± 0.30 2.0 (for orthogonal) 2.5 (for non-orthogonal)
METAL 51 3.0 3.0 ± 0.50 3.0
HOLE0 41 3.0 2.0 ± 0.20 2.0
HOLE1 0 4.0 3.0 ± 0.25 3.0
HOLE2 1 3.0 2.0 ± 0.30 2.0
HOLEM 48 5.0 4.0 ± 0.50 4.0

The Poly MEMS process has some rules specific to how each of the masking levels interact with one another.

# Rule Min. value (µm) Purpose Required
A POLY0 spaces ANCHOR14.0 Ensures ANCHOR1 holes specified outside of POLY0 do not expose the polysilicon 0 layer.No
B POLY0 encloses ANCHOR14.0 Ensures ANCHOR1 holes specified within POLY0 do not extend beyond the edge of the polysilicon 0 layer.No
C POLY0 encloses POLY14.0 Ensures the polysilicon 0 layer acts as an effective ground plane for the polysilicon 1 layer.No
D POLY0 encloses POLY25.0 Ensures the polysilicon 0 layer acts as an effective ground plane for the polysilicon 2 layer.No
E POLY0 spaces ANCHOR25.0 Ensures ANCHOR2 holes specified outside of POLY0 do not expose the polysilicon 0 layer.No
F POLY0 encloses ANCHOR25.0 Ensures ANCHOR2 holes specified within POLY0 do not extend beyond the edge of the polysilicon 0 layer.No
G POLY1 encloses ANCHOR14.0 Ensures ANCHOR1 holes specified within POLY1 are completely filled by the polysilicon 1 layer.No
H POLY1 encloses POLY1_POLY2_VIA4.0 Ensures POLY1_POLY2_VIA holes specified within POLY1 don't extend beyond the edge of the polysilicon 1 layer.No
I POLY1 spaces POLY23.0 Ensures the polysilicon 1 and polysilicon 2 layers will not overlap.No
J POLY2 encloses ANCHOR25.0 Ensures ANCHOR2 holes specified within POLY2 are completely filled by the polysilicon 2 layer.No
K POLY1 spaces ANCHOR23.0 Ensures ANCHOR2 holes specified outside of POLY1 do not expose the polysilicon 1 layer.No
L POLY2 encloses POLY1_POLY2_VIA4.0 Ensures POLY1_POLY2_VIA holes specified within POLY2 are completely filled by the polysilicon 2 layer.No
M POLY2 encloses METAL3.0 Ensures the entirety of the metal layer only contacts the polysilicon 2 layer.No
N POLY1 encloses DIMPLE4.0 Ensures DIMPLE holes specified within POLY1 are completely filled by the polysilicon 1 layer.No
O POLY1 encloses POLY24.0 Ensures the edges of the polysilicon 1 and polysilicon 2 layers do not overlap.No
P POLY2 cuts inside POLY15.0 Ensures the edges of the polysilicon 1 and polysilicon 2 layers do overlap.No
Q POLY2 cuts outside POLY14.0 Ensures the etch of the polysilicon 2 layer does not accidentally etch the polysilicon 1 layer.No
R HOLE1 spaces itself2.0 - 30.0 Holes in the HOLE1 mask should be between 2 and 30 µm apart. This ensures release of polysilicon 1 structures.Yes
S HOLE2 spaces itself2.0 - 30.0 Holes in the HOLE2 mask should be between 2 and 30 µm apart. This ensures release of polysilicon 2 structures.Yes
T HOLE2 encloses HOLE12.0 Ensures good release results when holes are overlapping.No
U HOLEM encloses HOLE22.0 Ensures good release results when holes are overlapping.No
V Center points of overlapping holes are aligned.N/A Ensures good release results when holes are overlapping.No
Color legend for the example wafers

POLY0 spaces ANCHOR1 - A

Topographic, cross sectional, and isometric diagrams of a wafer showing an anchor hole through the oxide 1 layer to the nitride layer.

This rule ensures ANCHOR1 holes specified outside of POLY0 do not expose the polysilicon 0 layer.

POLY0 encloses ANCHOR1 - B

Topographic, cross sectional, and isometric diagrams of a wafer showing an anchor hole through the oxide 1 layer to the polysilicon 0 layer.

This rule ensures ANCHOR1 holes specified within POLY0 do not extend beyond the edge of the polysilicon 0 layer.

POLY0 encloses POLY1 - C

Topographic, cross sectional, and isometric diagrams of a wafer showing the polysilicon 1 layer fully enclosed by the polysilicon 0 layer.

This rule ensures the polysilicon 0 layer acts as an effective ground plane for the polysilicon 1 layer.

POLY0 encloses POLY2 - D

Topographic, cross sectional, and isometric diagrams of a wafer showing the polysilicon 2 layer fully enclosed by the polysilicon 0 layer.

This rule ensures the polysilicon 0 layer acts as an effective ground plane for the polysilicon 2 layer.

POLY0 spaces ANCHOR2 - E

Topographic, cross sectional, and isometric diagrams of a wafer showing an anchor hole from the oxide 2 layer to the nitride layer directly.

This rule ensures ANCHOR2 holes specified outside of POLY0 do not expose the polysilicon 0 layer.

POLY0 encloses ANCHOR2 - F

Topographic, cross sectional, and isometric diagrams of a wafer showing an anchor hole from the oxide 2 layer to the nitride layer through the polysilicon 0 layer.

This rule ensures ANCHOR2 holes specified within POLY0 do not extend beyond the edge of the polysilicon 0 layer.

POLY1 encloses ANCHOR1 - G

Topographic, cross sectional, and isometric diagrams of a wafer showing the polysilicon 1 layer fully enclosing the hole made by the ANCHOR1 mask.

This rule ensures ANCHOR1 holes specified within POLY1 are completely filled by the polysilicon 1 layer.

POLY1 encloses POLY1_POLY2_VIA - H

Topographic, cross sectional, and isometric diagrams of a wafer showing via holes in the oxide 2 layer fully enclosed by the polysilicon 0 layer.

This rule ensures POLY1_POLY2_VIA holes specified within POLY1 don't extend beyond the edge of the polysilicon 1 layer.

POLY1 spaces POLY2 - I

Topographic, cross sectional, and isometric diagrams of a wafer showing how far features in the polysilicon 1 & 2 layers must be to ensure they won't overlap.

This rule ensures the polysilicon 1 and polysilicon 2 layers will not overlap.

POLY2 encloses ANCHOR2 - J

Topographic, cross sectional, and isometric diagrams of a wafer showing the polysilicon 2 layer fully enclosing the hole made by the ANCHOR2 mask.

This rule ensures ANCHOR2 holes specified within POLY2 are completely filled by the polysilicon 2 layer.

POLY1 spaces ANCHOR2 - K

Topographic, cross sectional, and isometric diagrams of a wafer showing how far features in the polysilicon 1 layer should be from holes made by the ANCHOR2 mask.

This rule ensures ANCHOR2 holes specified outside of POLY1 do not expose the polysilicon 1 layer.

POLY2 encloses POLY1_POLY2_VIA - L

Topographic, cross sectional, and isometric diagrams of a wafer showing the polysilicon 2 layer fully enclosing holes made by the POLY1_POLY2_VIA mask.

This rule ensures POLY1_POLY2_VIA holes specified within POLY2 are completely filled by the polysilicon 2 layer.

POLY2 encloses METAL - M

Topographic, cross sectional, and isometric diagrams of a wafer showing the polysilicon 2 layer fully enclosing a metal feature resting on top of it.

This rule ensures the entirety of the metal layer only contacts the polysilicon 2 layer.

POLY1 encloses DIMPLE - N

Topographic, cross sectional, and isometric diagrams of a wafer showing the polysilicon 1 layer fully enclosing the holes created by the DIMPLE mask.

This rule ensures DIMPLE holes specified within POLY1 are completely filled by the polysilicon 1 layer.

POLY1 encloses POLY2 - O

Topographic, cross sectional, and isometric diagrams of a wafer showing a feature in the polysilicon 2 layer fully enclosed by the polysilicon 1 layer beneath it.

This rule ensures the edges of the polysilicon 1 and polysilicon 2 layers do not overlap.

POLY2 cuts inside POLY1 - P

Topographic, cross sectional, and isometric diagrams of a wafer showing a feature in the polysilicon 2 layer partially overlapping the polysilicon 1 layer, with a minimum amount extending into the interior.

This rule ensures the edges of the polysilicon 1 and polysilicon 2 layers do overlap.

POLY2 cuts outside POLY1 - Q

Topographic, cross sectional, and isometric diagrams of a wafer showing a feature in the polysilicon 2 layer partially overlapping the polysilicon 1 layer, with a minimum amount extending outside.

This rule ensures the etch of the polysilicon 2 layer does not accidentally etch the polysilicon 1 layer.

HOLE1 spaces itself - R

Topographic, cross sectional, and isometric diagrams of a wafer showing the distance requirement for holes in the polysilicon 1 layer to ensure a feature releases from the layers below.

Holes in the HOLE1 mask should be between 2 and 30 µm apart. This ensures release of polysilicon 1 structures.

HOLE2 spaces itself - S

Topographic, cross sectional, and isometric diagrams of a wafer showing the distance requirement for holes in the polysilicon 2 layer to ensure a feature releases from the layers below.

Holes in the HOLE2 mask should be between 2 and 30 µm apart. This ensures release of polysilicon 2 structures.

HOLE2 encloses HOLE1 - T

Topographic, cross sectional, and isometric diagrams of a wafer showing how holes specified in the polysilicon 1 & 2 layers must overlap to ensure features don't bleed into one another.

This rule ensures good release results when holes are overlapping.

HOLEM encloses HOLE2 - U

Topographic, cross sectional, and isometric diagrams of a wafer showing how holes specified in the polysilicon 2 and metal layers must overlap to ensure features don't bleed into one another.

This rule ensures good release results when holes are overlapping.

Center points of overlapping holes are aligned - V

Topographic, cross sectional, and isometric diagrams of a wafer showing how holes specified in stacked layers must be aligned to ensure features don't bleed into one another.

This rule ensures good release results when holes are overlapping.