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Poly Process Overview

The Poly MEMS process uses eight masks to pattern and etch the wafer layers. The process uses 6 in wide, 10 µm thick, n-type, single-side polished silicon-on-insulator (SOI) wafers.

Color legend of the various layers used in the Poly MEMS process


Poly process step.

Step 1

The top silicon layer is doped with PSG.


Poly process step.

Step 2

The PSG is removed and replaced with a 600 nm silicon nitride layer using low pressure chemical vapor deposition (LPCVD).


Poly process step.

Step 3

A 500 nm polysilicon film is deposited onto the nitride layer using LPCVD—this is the polysilicon 0 layer.


Poly process step.

Step 4

The top of the wafer is coated in photoresist.


Poly process step.

Step 5

The photoresist is patterned with the light field POLY0 mask.


Poly process step.

Step 6

The patterned photoresist guides the etch of the polysilicon 0 layer—this is a plasma etch.


Poly process step.

Step 7

The photoresist is chemically removed with a solvent bath.


Poly process step.

Step 8

A 2.0 µm PSG layer is deposited by LPCVD and annealed at 1050°C for 1 hour in nitrogen gas—this is the oxide 1 layer.


Poly process step.

Step 9

The top of the wafer is coated in photoresist.


Poly process step.

Step 10

The photoresist is patterned with the dark field DIMPLES mask.


Poly process step.

Step 11

The patterned photoresist guides the etch of the oxide 1 layer to a nominal depth of 0.75 µm—this is a RIE etch.


Poly process step.

Step 12

The photoresist is chemically removed with a solvent bath.


Poly process step.

Step 13

A fresh coat of photoresist is applied to the top of the wafer.


Poly process step.

Step 14

The photoresist is patterned with the dark field ANCHOR1 mask.


Poly process step.

Step 15

The patterned photoresist guides the etch of the oxide 1 layer—this is a RIE etch.


Poly process step.

Step 16

The photoresist is chemically removed with a solvent bath.


Poly process step.

Step 17

A 2.0 µm layer of undoped polysilicon is deposited by LPCVD—this is the polysilicon 1 layer.


Poly process step.

Step 18

A 0.2 µm layer of PSG is deposited on the top of the wafer and annealed at 1050°C for 1 hour in nitrogen gas.


Poly process step.

Step 19

The wafer is coated in photoresist again.


Poly process step.

Step 20

The photoresist is patterned with the light field POLY1 mask.


Poly process step.

Step 21

The patterned photoresist guides the etch of the PSG and polysilicon 1 layers—these are plasma and RIE etches respectively.


Poly process step.

Step 22

The photoresist is chemically removed with a solvent bath and the remaining PSG is removed with a RIE etch.


Poly process step.

Step 23

A 0.75 µm PSG layer is deposited by LPCVD on the top of the wafer and annealed at 1050°C for 1 hour in nitrogen gas—this is the oxide 2 layer.


Poly process step.

Step 24

The top of the wafer is coated in photoresist.


Poly process step.

Step 25

The photoresist is patterned with the dark field POLY1_POLY2_VIA mask.


Poly process step.

Step 26

The patterned photoresist guides the etch of the oxide 2 layer—this is a RIE etch.


Poly process step.

Step 27

The photoresist is replaced with a fresh coat.


Poly process step.

Step 28

The photoresist is patterned with the dark field ANCHOR2 mask.


Poly process step.

Step 29

The patterned photoresist guides the etch of the oxide 1 & 2 layers—this is a RIE etch. This etch can go through the polysilicon 0 layer to expose the nitride layer, if desired.


Poly process step.

Step 30

The photoresist is chemically removed with a solvent bath.


Poly process step.

Step 31

A 1.5 µm layer of undoped polysilicon is deposited via LPCVD—this is the polysilicon 2 layer.


Poly process step.

Step 32

A 0.2 µm layer of PSG is deposited on the top of the wafer and annealed at 1050°C for 1 hour in nitrogen gas.


Poly process step.

Step 33

The top of the wafer is coated in photoresist.


Poly process step.

Step 34

The photoresist is patterned with the light field POLY2 mask.


Poly process step.

Step 35

The patterned photoresist guides the etch of the PSG and polysilicon 2 layers—these are plasma and RIE etches respectively.


Poly process step.

Step 36

The photoresist is chemically removed with a solvent bath and the remaining PSG is removed with a RIE etch.


Poly process step.

Step 37

A layer of photoresist is applied to the top of the wafer.


Poly process step.

Step 38

The photoresist is patterned with the light field METAL mask.


Poly process step.

Step 39

The patterned photoresist guides the deposition of the metal layer—this layer consists of gold and chrome.


Poly process step.

Step 40

The photoresist is chemically removed with a solvent bath.


Poly process step.

The wafer is ready to be shipped.

The customer can remove the oxide layers on their own by immersing the chip in a bath of 49% HF at room temperature for 1.5–2 minutes. This is followed by several minutes in DI water and then isopropyl alcohol to reduce stiction, followed by at least 10 minutes in an oven at 110°C.


Poly process step.Example wafer after release. The release can also be done by Science for a fee.