There are three primary masks that are each associated with one of the wafer levels outlined below. The OUTLINE, TAB, RELEASE, and XZONE masks are extra masking levels that etch all layers on the wafer in preparation for the final release.
| Material layer | Lithography mask name | Field type | Lithography purpose |
|---|---|---|---|
| Metal1 | METAL1 | light | Defines the geometry of metal for electrical connections. Metal is 20 nm Ti, 20 nm Pt, 150 nm Au, 20 nm Pt, and 20 nm Ti. |
| Polyimide 1 | OUTLINE1 | dark | Defines the final geometry to be released. |
| Polyimide 1 | OUTLINE2 | dark | Defines the etch on either side of the connective tabs and the perimeter of the release area. |
| Polyimide 1 | TAB | light | Defines connective tabs to release area. |
| Polyimide 2 | VIA | dark | Defines via through holes from the polyimide 2 layer to the polyimide 1 layer. |
| Top metal | TOPMETAL | light | Defines the geometry of metal for electrical connections. Metal is 10 nm Ti and 90 nm Pt. |
| Substrate | RELEASE | light | Defines the area for laser release. |
| Substrate | XZONE | dark | Defines an exclusion zone during laser release. |
| Substrate | - | - | The substrate layer is removed by the end of the process. |
The below table summarizes Science’s naming conventions and design limitations for each masking level.
| Mnemonic mask name | GDS mask number | Min. feature width (µm) | Min. space (µm) |
|---|---|---|---|
| METAL1 | 10 | 4 | 6 |
| VIA | 20 | 20 | 20 |
| OUTLINE1 | 20 | 20 | 20 |
| OUTLINE2 | 21 | - | - |
| TAB | 22 | - | - |
| TOPMETAL | 30 | 4 | 6 |
| RELEASE | 40 | - | - |
| XZONE | 41 | - | - |
OUTLINE, TAB, RELEASE, and XZONE masking levels
The final trench etch that separates the release area from the rest of the wafer is defined by the OUTLINE1 masking level which is itself defined by the TAB and OUTLINE2 masking levels. A full explanation of connective tabs can be found in the design standards section.
Double patterning
An additional mask can be created for a fee to improve the minimum feature and minimum spacing to 2.5 µm. For details on this process, please email foundry@science.xyz.
Mask to mask design rules
The TFE process has some rules specific to how each of the masks interact with one another.
| # | Rule | Min. Value (µm) | Function | Required? |
|---|---|---|---|---|
| A | TOPMETAL encloses VIA | 10 | This ensures the metal layer completely fills the VIA mask hole. | No |
| B | METAL1 encloses VIA | 10 | This ensures the VIA mask only etches over the metal 1 layer for electrodes. | No |
| C | OUTLINE1 spaces METAL1 | 200 | This guideline ensures any metal traces are appropriately far from the perimeter of OUTLINE1. | No |
| D | OUTLINE1 alignment to METAL1 | ± 3 | The alignment tolerance between the OUTLINE1 and METAL1 masks is ± 3 µm. | No |
| This example wafer features:
|
TOPMETAL encloses VIA - A
This guideline ensures the top metal layer completely fills the VIA mask hole.
METAL1 encloses VIA - B
This guideline ensures that the VIA mask only etches over the metal 1 layer for electrodes.
OUTLINE1 spaces METAL1 - C
This guideline ensures any metal traces are appropriately far from the perimeter of OUTLINE1.
OUTLINE1 layer alignment to METAL1 layer - D
This guideline ensures the alignment tolerance keeps the OUTLINE1 etch over the metal 1 layer.