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Thin Film Electrode Design Rules

There are three primary masks that are each associated with one of the wafer levels outlined below. The OUTLINE, TAB, RELEASE, and XZONE masks are extra masking levels that etch all layers on the wafer in preparation for the final release.

Material layer Lithography mask name Field type Lithography purpose
Metal1METAL1 light Defines the geometry of metal for electrical connections. Metal is 20 nm Ti, 20 nm Pt, 150 nm Au, 20 nm Pt, and 20 nm Ti.
Polyimide 1OUTLINE1 dark Defines the area to be released.
Polyimide 1TAB light Defines connective tabs to release area.
Polyimide 1OUTLINE2 dark Defines etch on either side of the connective tabs.
Polyimide 2VIA dark Defines via through holes from the polyimide 2 layer to the polyimide 1 layer.
Top metalTOPMETAL light Defines the geometry of metal for electrical connections. Metal is 10 nm Ti and 90 nm Pt.
SubstrateRELEASE light Defines the area for laser release.
SubstrateXZONE dark Defines an exclusion zone during laser release.
Substrate- - The substrate layer is removed by the end of the process.

The below table summarizes Science’s naming conventions and design limitations for each masking level.

Mneumonic mask nameGDS mask numberMin. feature width (µm)Min. space (µm)
METAL110 4 6
VIA20 20 20
OUTLINE120 20 20
TAB21 - -
OUTLINE222 - -
TOPMETAL30 4 6
RELEASE40 - -
XZONE41 - -
OUTLINE, TAB, RELEASE, and XZONE masking levels

The final trench etch that separates the release area from the rest of the wafer is defined by the OUTLINE1 masking level which is itself defined by the TAB and OUTLINE2 masking levels. A full explanation of connective tabs can be found in the design standards section.

Mask to mask design rules

The TFE process has some rules specific to how each of the masks interact with one another.

#Rule Min. Value (µm) Function Required?
ATOPMETAL encloses VIA10 This ensures the metal layer completely fills the VIA mask hole.No
BMETAL1 encloses VIA10 This ensures the VIA mask only etches over the metal 1 layer.No
CPolyimide 2 alignment to polyimide 1 layer± 3 The center of the polyimide 2 layer is deposited within ± 3 µm of the center of the polyimide 1 layer.No

Isometric diagram of an example wafer

This example wafer features:

  • an outline of a release area
  • tabs holding the area in place
  • electrode pads connected via metal traces

Color legend for the example wafer


TOPMETAL encloses VIA - A

Topographic and cross sectional diagrams of a wafer showing how far the top metal layer should extend beyond the VIA mask edge to ensure the layer completely fills the hole.

This guideline ensures the top metal layer completely fills the VIA mask hole.


METAL1 encloses VIA - B

Topographic and cross sectional diagrams of a wafer showing how far the metal 1 layer should extend beyond the VIA mask edge to ensure the etch only occurs over metal.

This guideline ensures the the VIA mask only etches over the metal 1 layer.


Polyimide 2 layer alignment to polyimide 1 layer - C

Topographic and cross sectional diagrams of a wafer showing the lateral alignment tolerance between polyimide layers.

The two polyimide layers are applied within a ± 3 µm tolerance.