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Design rules

Thin Film Electronics Design Rules

There are three primary masks that are each associated with one of the wafer levels outlined below. The OUTLINE, TAB, RELEASE, and XZONE masks are extra masking levels that etch all layers on the wafer in preparation for the final release.

Material layer Lithography mask name Field type Lithography purpose
Metal1METAL1 light Defines the geometry of metal for electrical connections. Metal is 20 nm Ti, 20 nm Pt, 150 nm Au, 20 nm Pt, and 20 nm Ti.
Polyimide 1OUTLINE1 dark Defines the final geometry to be released.
Polyimide 1OUTLINE2 dark Defines the etch on either side of the connective tabs and the perimeter of the release area.
Polyimide 1TAB light Defines connective tabs to release area.
Polyimide 2VIA dark Defines via through holes from the polyimide 2 layer to the polyimide 1 layer.
Top metalTOPMETAL light Defines the geometry of metal for electrical connections. Metal is 10 nm Ti and 90 nm Pt.
SubstrateRELEASE light Defines the area for laser release.
SubstrateXZONE dark Defines an exclusion zone during laser release.
Substrate- - The substrate layer is removed by the end of the process.

The below table summarizes Science’s naming conventions and design limitations for each masking level.

Mneumonic mask nameGDS mask numberMin. feature width (µm)Min. space (µm)
METAL110 4 6
VIA20 20 20
OUTLINE120 20 20
OUTLINE221 - -
TAB22 - -
TOPMETAL30 4 6
RELEASE40 - -
XZONE41 - -
OUTLINE, TAB, RELEASE, and XZONE masking levels

The final trench etch that separates the release area from the rest of the wafer is defined by the OUTLINE1 masking level which is itself defined by the TAB and OUTLINE2 masking levels. A full explanation of connective tabs can be found in the design standards section.

Double patterning

An additional mask can be created for a fee to improve the minimum feature and minimum spacing to 2.5 µm. For details on this process, please email foundry@science.xyz.

Mask to mask design rules

The TFE process has some rules specific to how each of the masks interact with one another.

#Rule Min. Value (µm) Function Required?
ATOPMETAL encloses VIA10 This ensures the metal layer completely fills the VIA mask hole.No
BMETAL1 encloses VIA10 This ensures the VIA mask only etches over the metal 1 layer for electrodes.No
COUTLINE1 spaces METAL1200 This guideline ensures any metal traces are appropriately far from the perimeter of OUTLINE1.No
DOUTLINE1 alignment to METAL1± 3 The alignment tolerance between the OUTLINE1 and METAL1 masks is ± 3 µm.No

Isometric diagram of an example wafer

This example wafer features:

  • an outline of a release area
  • tabs holding the area in place
  • electrode pads connected via metal traces

Color legend for the example wafer


TOPMETAL encloses VIA - A

Topographic and cross sectional diagrams of a wafer showing how far the top metal layer should extend beyond the VIA mask edge to ensure the layer completely fills the hole.

This guideline ensures the top metal layer completely fills the VIA mask hole.


METAL1 encloses VIA - B

Topographic and cross sectional diagrams of a wafer showing how far the metal 1 layer should extend beyond the VIA mask edge to ensure the etch only occurs over metal.

This guideline ensures the the VIA mask only etches over the metal 1 layer for electrodes.


OUTLINE1 spaces METAL1 - C

Topographic and cross sectional diagrams of a wafer showing the lateral alignment tolerance between the OUTLINE1 and METAL1 layers.

This guideline ensures any metal traces are appropriately far from the perimeter of OUTLINE1.


OUTLINE1 layer alignment to METAL1 layer - D

Topographic and cross sectional diagrams of a wafer showing the lateral alignment tolerance between the OUTLINE1 and METAL1 layers.

This guideline ensures the alignment tolerance keeps the OUTLINE1 etch over the metal 1 layer.