Docs - Science

The TFE process uses three masks and a variety of masking levels to pattern and etch the wafer layers. The process uses double-side polished, fused silica wafers that measure 6 in and 500 µm thick. Diagrams below are not shown to scale, sizes have been exaggerated for educational purposes.

Color legend for diagrams below

		Step 1 A 5 µm layer of polyimide is deposited onto the sapphire substrate via spin coating. The wafer is then cured in nitrogen gas for 30 minutes at 350°C.

A layer of polyimide is shown atop a layer of substrate.

Step 1

A 5 µm layer of polyimide is deposited onto the sapphire substrate via spin coating. The wafer is then cured in nitrogen gas for 30 minutes at 350°C.

		Step 2 Two layers of resist are applied to the top of the wafer.

Two resist layers are shown atop a layer of polyimide which is shown atop a layer of substrate.

Step 2

Two layers of resist are applied to the top of the wafer.

		Step 3 The photoresist layers are patterned with the light field METAL1 mask.

A polyimide wafer is shown with two patterned layers of resist atop it.

Step 3

The photoresist layers are patterned with the light field METAL1 mask.

		Step 4 A 240 nm layer of pad metal is deposited on top of the wafer—this is composed of 20 nm Ti, 20 nm Pt, 160 nm Au, 20 nm Pt, and 20 nm Ti.

A stack of metal is shown sitting across a wafer with patterned resist.

Step 4

A 240 nm layer of pad metal is deposited on top of the wafer—this is composed of 20 nm Ti, 20 nm Pt, 160 nm Au, 20 nm Pt, and 20 nm Ti.

		Step 5 The photoresist is removed with a chemical strip.

A pattern of metal is shown sitting alone on a layer of polyimide.

Step 5

The photoresist is removed with a chemical strip.

		Step 6 A new layer of polyimide is applied across the top of the wafer.

A pattern of metal is shown sandwiched between two layers of polyimide.

Step 6

A new layer of polyimide is applied across the top of the wafer.

		Step 7 Two layers of resist are applied in the same pattern as the OUTLINE1 mask.

A pattern of resist is shown atop two polyimide layers that are sandwiching a layer of metal in an identical pattern.

Step 7

Two layers of resist are applied in the same pattern as the OUTLINE1 mask.

		Step 8 A thin layer of metal is applied to the top of the wafer as a hard mask.

A thin layer of metal is shown atop a wafer of polyimide and resist.

Step 8

A thin layer of metal is applied to the top of the wafer as a hard mask.

		Step 9 The two layers of resist are removed in a chemical strip.

A thin layer of metal is shown in a reverse pattern to the buried metal layer sandwiched between two polyimide layers.

Step 9

The two layers of resist are removed in a chemical strip.

		Step 10 The patterned metal hard mask guides the etch of the polyimide 2 layer while the OUTLINE1 masking level guides an etch through the full thickness of the wafer.

The previously buried metal layer is shown exposed after the second polyimide layer is etched away in an identical pattern.

Step 10

The patterned metal hard mask guides the etch of the polyimide 2 layer while the OUTLINE1 masking level guides an etch through the full thickness of the wafer.

		Step 11 A second etch removes the hard mask and the topmost layer of the pad metal stack.

The thin metal layer on top of the wafer has disappeared and action lines draw attention to the buried metal layer.

Step 11

A second etch removes the hard mask and the topmost layer of the pad metal stack.

		Step 12 Two layers of resist are applied across the top of the wafer.

Two new layers of resist are added.

Step 12

Two layers of resist are applied across the top of the wafer.

		Step 13 The photoresist is etched with the TOPMETAL mask.

The resist layers are shown with an etch pattern identical to the electrode sites.

Step 13

The photoresist is etched with the TOPMETAL mask.

		Step 14 The 100 nm top metal layer is applied across the top of the wafer—this is composed of 10 nm of Ti and 90 nm of Pt. The portion of the top metal layer that extends past the VIA masking level may not be electrically connected to the metal 1 layer.

A second layer of metal is shown deposited across the top of the wafer and into the etch holes.

Step 14

The 100 nm top metal layer is applied across the top of the wafer—this is composed of 10 nm of Ti and 90 nm of Pt. The portion of the top metal layer that extends past the VIA masking level may not be electrically connected to the metal 1 layer.

		Step 15 The layers of resist are removed with a chemical etch.

The resist layers are removed, leaving just two metal layers enclosed on three sides by polyimide atop the substrate layer.

Step 15

The layers of resist are removed with a chemical etch.

		Step 16 A laser release removes the bottom substrate from under the area according to the RELEASE masking level.

The bottom substrate layer is removed, leaving just the metal and polyimide layers.

Step 16

A laser release removes the bottom substrate from under the area according to the RELEASE masking level.

Thin Film Electrode Process Overview