There are five primary masks that are each associated with one of the wafer levels outlined below. The SOIHOLE mask is an extra, special-use masking level that helps designers define holes in the silicon layer. The buried oxide layer has no mask that directly patterns it.
| Material layer | Lithography mask name | Field type | Lithography purpose |
|---|---|---|---|
| Pad oxide | PADOXIDE | light | Provides metal for piezoelectric devices. |
| Piezoelectric film | PZFILM | light | Electrically isolates piezoelectric and pad metal layers from the silicon layer. |
| Pad metal | PADMETAL | light | Defines the geometry of metal for electrical connections. Metal is 20 nm Cr and 1000 nm Al. |
| Silicon | SOI | light | Defines structures in the silicon layer. |
| Silicon | SOIHOLE | dark | Defines holes in the silicon layer. |
| Buried oxide | - | - | - |
| Substrate | TRENCH | dark | Defines through-hole structures in the substrate layer. |
The below table summarizes Science’s naming conventions and design limitations for each masking level.
| Mneumonic mask name | GDS mask number | Min. feature length (µm) | Min. space (µm) | Max. feature length (µm) | Max. etched area mm² |
|---|---|---|---|---|---|
| PADOXIDE | 10 | 5 | 5 | Unlimited | N/A |
| PZFILM | 20 | 10 | 10 | 5000 | N/A |
| PADMETAL | 30 | 5 | 5 | 5000 | N/A |
| SOI | 40 | See note below ↓ | See note below ↓ | See note below ↓ | 33 |
| SOIHOLE | 41 | 3 | 3 | - | - |
| TRENCH | 50 | 200 | 200 | 5000 | 25 |
SOI mask notes
Features in the SOI layer with a width greater than 6 µm have no maximum length. Silicon features in the SOI layer that are less than 6 µm wide may curl out of plane from the substrated due to the intrinsic stresses in the silicon layer. To minimize the possibility of curling, Science recommends a maximum length of 500 µm if the structure is anchored at both ends and 100 µm if it is anchored at only one end.
Features and spaces on non-orthogonal axes may not print on wafers at their nominal sizes due to the pixelation of the 0.25 µm photomask resolution. This may cause bridging between closely spaced features in the SOI layer. Science recommends a slightly higher minimum feature and minimum space requirement for non-orthogonal features at 2.5 µm instead of the 2 µm used with orthogonal features.
Mask to mask design rules
The Piezo MEMS process has some rules specific to how each of the masking levels interact with one another.
| # | Rule | Min. Value (µm) | Function | Required? |
|---|---|---|---|---|
| A | SOI encloses PZFILM | 5 | This rule ensures the piezoelectric film is not accidentally exposed to the SOI mask etch. | Yes |
| B | SOI encloses PADMETAL | 3 | This rule ensures the pad metal layer is not accidentally exposed to the SOI mask etch. | Yes |
| C | SOI space to TRENCH | 50 | This guideline ensures the edge of the substrate does not undermine the edge of the silicon during the TRENCH etching process. | No |
| D | SOI encloses PADOX | 3 | This guideline ensures the pad oxide layer does not cross into the SOI mask etch. | No |
| E | SOI encloses PADOX features over TRENCH | 10 | This guideline ensures the pad oxide layer is not exposed to the TRENCH etch. | No |
| F | PADOX spaces PZFILM | 5 | This guideline ensures the piezoelectric layer does not interact with the PADOXIDE mask. | No |
| G | PADOX spaces PADMETAL | 5 | This guideline ensures the pad metal layer does not interact with the PADOXIDE mask. | No |
| H | PADOX encloses PZFILM | 5 | This guideline ensures the piezoelectric film only touches the pad oxide layer and does not touch the silicon layer. | No |
| I | PADOX encloses PADMETAL | 4 | This guideline ensures the pad metal layer only touches the pad oxide layer and does not touch the silicon layer. | No |
| J | PZFILM encloses PADMETAL | 4 | This guideline ensures the pad metal layer only touches the piezoelectric film. | No |
| K | PADMETAL cuts inside PZFILM | 5 | This guideline ensures that the pad metal layer touches the piezoelectric film for routing purposes. | No |
Each of the design rules is displayed in one of the example wafers below. Topographic and cross-sectional views are provided for each design rule individually.
 |  |  |
 |
|---|
SOI encloses PZFILM - A
This rule ensures the piezoelectric film is not accidentally exposed to the SOI mask etch.
SOI encloses PADMETAL - B
This rule ensures the pad metal layer is not accidentally exposed to the SOI mask etch.
SOI space to TRENCH - C
This guideline ensures the edge of the substrate does not undermine the edge of the silicon during the TRENCH etching process.
SOI encloses PADOX - D
This guideline ensures the pad oxide layer does not cross into the SOI mask etch.
SOI encloses PADOX features over TRENCH - E
This guideline ensures the pad oxide layer is not exposed to the TRENCH etch.
PADOX spaces PZFILM - F
This guideline ensures the piezoelectric layer does not interact with the PADOXIDE mask.
PADOX spaces PADMETAL - G
This guideline ensures the pad metal layer does not interact with the PADOXIDE mask.
PADOX encloses PZFILM - H
This guideline ensures the piezoelectric film only touches the pad oxide layer and does not touch the silicon layer.
PADOX encloses PADMETAL - I
This guideline ensures the pad metal layer only touches the pad oxide layer and does not touch the silicon layer.
PZFILM encloses PADMETAL - J
This guideline ensures the pad metal layer only touches the piezoelectric film.
PADMETAL cuts inside PZFILM - K
This guideline ensures that the pad metal layer touches the piezoelectric film for routing purposes.