Loading...

Design rules

SOI Design Rules

There are four primary masks that are each associated with one of the wafer levels outlined below. The SOIHOLE mask is an extra, special-use masking level that helps designers define holes in the silicon layer. The buried oxide layer has no mask that directly patterns it, but it can be etched using the TRENCH mask and DRIE techniques.

Material layer Lithography mask name Field type Lithography purpose
Pad metalPADMETAL light Defines the geometry of metal for electrical connections. Metal is 20 nm Cr and 500 nm Au.
SiliconSOI light Defines structures in the silicon layer.
SiliconSOIHOLE dark Defines holes in the silicon layer.
Buried oxide- - -
SubstrateTRENCH dark Defines through-hole structures in the substrate layer.
Blanket metalBLANKETMETAL dark Defines the geometry of metal to be deposited through a shadow mask. Metal is 50 nm Cr and 600 nm Au.

The below table summarizes Science’s naming conventions and design limitations for each masking levels.

Mneumonic mask nameGDS mask numberMin. feature length (µm)Min. space (µm)Max. feature length (µm)Max. etched area mm²
PADMETAL5 3 3 5000 N/A
SOI10 See note below ↓ See note below ↓ See note below ↓33
SOIHOLE11 3 3 - -
TRENCH20 200 200 5000 25
BLANKETMETAL30 100 100 5000 20
SOI mask notes

Features in the SOI layer with a width greater than 6 µm have no maximum length. Silicon features in the SOI layer that are less than 6 µm wide may curl out of plane from the substrate due to the intrinsic stresses in the silicon layer. To minimize the possibility of curling, Science recommends a maximum length of 500 µm if the structure is anchored at both ends and 100 µm if it is anchored at only one end.

Features and spaces on non-orthogonal axes may not print on wafers at their nominal sizes due to the pixelation of the 0.25 µm photomask resolution. This may cause bridging between closely spaced features in the SOI layer. Science recommends a slightly higher minimum feature and minimum space requirement for non-orthogonal featuers at 2.5 µm instead of the 2 µm used with orthogonal features.

Mask to mask design rules

The SOI MEMS process has some rules specific to how each of the masking levels interact with one another.

#Rule Min. Value (µm) Function Required?
ASOI encloses PADMETAL3 This rule ensures the pad metal layer is not accidentally exposed to the SOI mask etch.Yes
BSOI spaces TRENCH50 This guideline ensures the edge of the substrate does not undermine the edge of the silicon during the TRENCH etching process.No
CSOI feature size is at least10 This guideline, together with rule B, ensures the silicon stucture is anchored to the substrate layer.No
DTRENCH encloses silicon structure5 This guideline ensures the silicon stucture is released from the substrate layer.No
EBLANKETMETAL alignment to SOI± 35 The center of the blanket metal layer is deposited with a ± 35 µm tolerance.No
FShadow mask alignment to SOI± 40 The center of the shadow mask is bonded with a ± 40 µm tolerance.No

Isometric diagram of an example wafer

This example wafer features:

  • a pad metal structure
  • a blanket metal structure
  • a silicon layer etch and “released” structure
  • a substrate layer etch

Color legend for the example wafer


SOI encloses PADMETAL - A

Topographic and cross sectional diagrams of a wafer showing how far pad metal features must be from the SOI mask edge

This rule ensures the pad metal layer is not accidentally exposed to the SOI mask etch.


SOI spaces TRENCH - B

Topographic and cross sectional diagrams of a wafer showing how far silicon features should be from the TRENCH mask edge

This guideline ensures the edge of the substrate does not undermine the edge of the silicon during the TRENCH etching process.


SOI feature size is at least - C

Topographic and cross sectional diagrams of a wafer showing how large a silicon feature must be to ensure it is anchored

This guideline, together with rule B, ensures the silicon stucture is anchored to the substrate layer.


TRENCH encloses silicon structure - D

Topographic and cross sectional diagrams of a wafer showing how the TRENCH mask must enclose a silicon structure to ensure it is released

This guideline ensures the silicon stucture is released from the substrate layer.


BLANKETMETAL alignment to SOI - E

Topographic and cross sectional diagrams of a wafer showing alignment tolerance of the blanket metal layer

The center of the blanket metal layer is deposited with a ± 35 µm tolerance.


Shadowmask alignment to SOI - F

Topographic and cross sectional diagrams of a wafer showing alignment tolerance of the shadow mask

The center of the shadow mask is bonded with a ± 40 µm tolerance.