The SOI MEMS process uses four masks to pattern and etch the wafer layers. The process uses 6 in wide, n-type, double-side polished silicon-on-insulator (SOI) wafers with a 25 µm thick device layer. Diagrams below are not shown to scale, sizes have been exaggerated for educational purposes.
| Step 1 The top silicon layer is doped with PSG. |
| Step 2 The PSG is removed and replaced with a coating of photoresist. |
| Step 3 The photoresist is patterned by the light field PADMETAL mask. |
| Step 4 A layer of 20 nm Cr and 500 nm Au is deposited across the top of the wafer—this is the pad metal layer. |
| Step 5 A liftoff technique is used to remove all the pad metal that is not within the gaps of photoresist. |
| Step 6 The remaining photoresist is dissolved in a wet chemical etch. |
| Step 7 The wafer is once again coated with photoresist. |
| Step 8 The photoresist is patterned with the light field SOI mask. |
| Step 9 The patterned photoresist guides the etch of the silicon layer—this is a DRIE etch. |
| Step 10 The remaining photoresist is chemically stripped away. |
| Step 11 A protective polyimide layer is applied to the top surface of the wafer while the bottom side is worked on. |
| Step 12 A layer of photoresist is applied to the bottom of the wafer. |
| Step 13 The photoresist is patterned with the dark field TRENCH mask. |
| Step 14 The patterned photoresist guides the etch of the bottom oxide—this is a RIE etch. |
| Step 15 The photoresist guides the etch of the substrate layer—this is a DRIE etch and causes a “blow out” towards the buried oxide layer. |
| Step 16 The patterned substrate guides the etch of the buried oxide layer—this is a wet oxide etch. |
| Step 17 The protective polyimide material is stripped away with a dry etch process. This “releases” any mechanical structures in the silicon layer that are located over through-holes in the substrate layer. |
| Step 18 The photoresist is chemically stripped away. |
| Step 19 The remaining oxide is removed with a HF vapor process. This process causes a slight undercut (1.9 µm) of the buried oxide layer to prevent metal shorting between layers. |
| Step 20 A second silicon wafer is used to create a shadow mask for the blanket metal layer. The shadow mask has standoffs to minimize contact area with the wafer once it is applied. |
| Step 21 Photoresist is applied to the top of the shadowmask. |
| Step 22 The photoresist is patterned with the dark field BLANKETMETAL mask. |
| Step 23 The patterned photoresist guides the etch of the shadow mask—this is a DRIE etch. |
| Step 24 The photoresist is chemically stripped away. |
| Step 25 The shadow mask is aligned and temporarily bonded to the edge of the silicon layer. |
| Step 26 The blanket metal layer is deposited through the gaps of the shadow mask via electron beam evaporation. |
| Step 27 The shadow mask is removed. The wafer is now ready to be cut, packaged, and shipped. |
